Semiconductor memory device having memory cell and reference cell connected to same sense amplifier and method of reading data thereof

1. A semiconductor memory device, comprising:

a sense amplifier;

first and second bit lines connected to the sense amplifier;

a reference cell coupled to the first bit line,

a memory cell coupled to the second bit line; and

a dummy cell, simultaneously with the reference cell, written with a reference potential;

wherein said reference cell includes a first capacitor to be written with the reference potential, and said dummy cell includes a second capacitor to be written with the reference potential; the semiconductor memory device, further comprising:

a potential line for providing the reference potential;

a first transistor coupled between the potential line and the first capacitor; and

a second transistor coupled to the potential line and the second capacitor.

2. The semiconductor memory device according to claim 1 , further comprising a

a word line connected to gates of the first and second transistors.

3. The semiconductor memory device according to claim 1 , further comprising:

a first word line connected to a gate of the first transistor; and a second word line independently provided from the first word line and connected to a gate of the second transistor.

4. A method of reading data from a semiconductor memory device, comprising:

simultaneously writing a reference potential to a reference cell and a dummy cell, said reference cell coupled to a sense amplifier, said dummy cell independently provided from said sense amplifier; and

comparing the reference potential of said reference cell with a potential in a memory cell by using the sense amplifier;

wherein the simultaneously writing of the reference potential to the reference and dummy cells is performed by writing the reference potential to a first capacitor provided in the reference cell, and writing the reference potential to a second capacitor provided in the dummy cell;

wherein the simultaneously writing of the reference potential to the reference and dummy cells is performed by writing the reference potential on a reference potential line to the first capacitor via a first transistor, and the reference potential to the second capacitor via a second transistor.

5. The method according to claim 4 , comprising:

simultaneously activating first and second word lines connected to the first and second transistors, respectively.

6. The method according to claim 4 , comprising:

activating a word line connected to the first and second transistors.