Bias circuit having second current path to bandgap reference during power-on

1. A bias circuit having a bandgap reference, comprising:

a first current path supplying a drive current to the bandgap reference; and

a second current path supplying a current to the bandgap reference for a predetermined period of time after power-on,

wherein the first current path comprises a first resistor element.

2. The bias circuit according to claim 1 , wherein the second current path is connected in parallel with the first current path, and the second current path serves as a bypass current path for the first current path for the predetermined period of time.

3. The bias circuit according to claim 1 , wherein the first current path further comprises a first transistor having an on-resistance smaller than a resistance value of the first resistor element, the first transistor being connected in parallel with the first resistor element.

4. The bias circuit according to claim 1 , wherein the second current path comprises a second transistor having an on-resistance smaller than a resistance value of the first resistor element.

5. The bias circuit according to claim 4 , wherein the predetermined period of time is determined according to a second resistor element and a capacitor element that are connected between a control terminal of the second transistor and a power supply.

6. The bias circuit according to claim 3 , wherein the first transistor supplies a drive current to the bandgap reference after the predetermined period of time.

7. The bias circuit according to claim 1 , wherein said predetermined period of time substantially corresponds to a startup period of said bandgap reference.

8. A bias circuit, comprising:

a bandgap reference circuit;

a first current path supplying a drive current to the bandgap reference circuit; and

a second current path in parallel to said first current path, said second current path supplying additional startup current to the bandgap reference circuit for a predetermined period of time after a power-on,

wherein said first current path comprises a drive current resistor in parallel with a transistor controlled by a voltage regulator circuit.

9. The bias circuit of claim 8 , wherein said predetermined period of time substantially corresponds to a startup time of said bandgap reference circuit.

10. The bias circuit of claim 8 , wherein said second current path comprises a startup transistor controlled by a capacitor/resistor circuit, said capacitor/resistor circuit conducting current substantially only during said power-on.

11. The bias circuit of claim 10 , wherein sizes of said capacitor and resistor in said capacitor/resistor circuit are preselected to correspond to a startup time of said bandgap reference circuit.

12. The bias circuit of claim 8 , wherein an impedance of said second current path during said power-on period is smaller than an impedance of said first current path.

13. A semiconductor integrated circuit, comprising:

an internal circuit;

a bandgap reference circuit providing a bias to said internal circuit; and

a bias circuit for said bandgap reference circuit,

wherein said bias circuit comprises:

a first current path supplying a drive current to the bandgap reference circuit; and

a second current path in parallel to said first current path, said second current path supplying additional startup current to the bandgap reference circuit for a predetermined period of time after a power-on, and

wherein said second current path comprises a startup transistor controlled by a capacitor/resistor circuit, said capacitor/resistor circuit conducting current substantially only during said power-on.

14. The semiconductor integrated circuit of claim 13 , wherein said predetermined period of time substantially corresponds to a startup time of said bandgap reference circuit.

15. The semiconductor integrated circuit of claim 13 , wherein an impedance of said second current path during said power-on period is smaller than an impedance of said first current path.

16. The semiconductor integrated circuit of claim 13 , wherein said first current path comprises a drive current resistor in parallel with a transistor controlled by a voltage regulator circuit.

17. The semiconductor integrated circuit of claim 13 , wherein sizes of said capacitor and resistor in said capacitor/resistor circuit are preselected to correspond to a startup time of said bandgap reference circuit.