Standalone thin film memory
View Patent ↗A standalone memory device includes thin-film peripheral circuitry, including decoding circuitry. The standalone thin film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass. The memory is configured for operation with an external memory controller.
1. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the thin-film peripheral circuitry comprises a thin film address decoder, the thin film address decoder comprising a three-terminal ovonic threshold switch.
2. The memory device of claim 1 , wherein the thin-film memory cells include an ovonic threshold switch isolation device.
3. The memory device of claim 1 , wherein the thin-film memory cells comprise programmable resistance devices.
4. The memory device of claim 3 , wherein the thin-film memory cells comprise phase change devices.
5. The memory device of claim 4 , wherein the thin-film memory cells comprise chalcogenide devices.
6. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the peripheral circuitry includes thin film row drivers and thin film column drivers, the drivers comprising three-terminal ovonic threshold switches.
7. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the peripheral circuitry comprises data input devices configured to receive signals from a device other than the memory device, said input devices including ovonic threshold switches.
8. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the peripheral circuitry comprises data output devices configured to transmit signals to a device other than the memory device, said output devices including ovonic threshold switches.
9. A standalone memory device, comprising:
thin-film memory cells arranged in an array;
a thin film isolation device configured to isolate a thin film memory cell and to thereby block inadvertent access to the cell;
a thin film address decoder configured to accept address information and to access a memory cell defined by the address information;
thin film data input devices configured to receive signals from a device other than the memory device;
thin film data output devices configured to transmit signals to a device other than the memory device;
thin film row and column drivers configured to operate under control of said thin film decoder to access a memory cell; and
a thin film sense amplifier configured to sense the state of a memory cell accessed by said thin-film address decoder and row and column drivers.
10. The memory device of claim 9 , wherein the thin film address decoder comprises three-terminal ovonic threshold switches.
11. The memory device of claim 9 , wherein the input devices comprise three-terminal ovonic threshold switches.
12. The memory device of claim 9 , wherein the output devices comprise three-terminal ovonic threshold switches.
13. The memory device of claim 9 , wherein the row and column drivers comprise three-terminal ovonic threshold switches.
14. The memory device of claim 9 , further comprising four-phase logic circuitry.
15. The memory device of claim 14 , further comprising three-terminal ovonic threshold switch timing and control circuitry.
16. The memory device of claim 9 , wherein the thin-film memory cells include an ovonic threshold switch isolation device.
17. The memory device of claim 9 , wherein the thin-film memory cells comprise programmable resistance devices.
18. The memory device of claim 17 , wherein the thin-film memory cells comprise phase change devices.
19. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the thin film peripheral circuitry is configured to operate with external test circuitry.
20. The memory device of claim 19 , wherein the peripheral circuitry includes test pads configured to accept test signals from external test circuitry.
21. The memory device of claim 19 , wherein the peripheral circuitry includes test registers configured to receive input from an external test device.
22. The memory device of claim 19 , wherein the peripheral circuitry include reconfiguration registers configured to receive input from an external test device.
23. The memory device of claim 19 , wherein the peripheral circuitry includes redundant memory cells configured for mapping into the memory device's memory map under control of an external test device.
24. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory, wherein the peripheral circuitry is configured to operate with an external memory controller and wherein the memory is configured to operate with external circuitry that includes single-crystal electronic devices, the memory being configured to receive a voltage reference signal from the external circuitry.
25. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the peripheral circuitry is configured to operate with an external memory controller and wherein the memory is configured to operate with external circuitry that includes single-crystal electronic devices, the memory being configured to transmit an analog representation of a memory cell value to the external circuitry for conversion to a digital value.
26. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the memory includes no single-crystal devices.
27. The memory device of claim 26 , wherein the thin-film memory cells include an ovonic threshold switch isolation device.
28. The memory device of claim 26 , wherein the thin-film memory cells comprise programmable resistance devices.
29. The memory device of claim 28 , wherein the thin-film memory cells comprise phase change devices.
30. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, and a substrate upon which the memory cells and peripheral circuitry are formed, the substrate being a non-single crystal material.
31. The memory device of claim 30 , wherein the substrate is a ceramic material.
32. The memory device of claim 30 , wherein the substrate is a fiberglass material.
33. The memory device of claim 30 , wherein the substrate is a glass material.
34. The memory device of claim 30 , wherein the substrate is a quartz material.
35. The memory device of claim 30 , wherein the thin-film memory cells include an ovonic threshold switch isolation device.
36. The memory device of claim 30 , wherein the thin-film memory cells comprise programmable resistance devices.
37. The memory device of claim 36 , wherein the thin-film memory cells comprise phase change devices.
38. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the memory includes more than 128 Mbits and the memory devices are formed with fewer than 20 mask steps.
39. The memory device of claim 38 , wherein the memory includes more than 128 Mbits and the memory devices are formed with fewer than 15 mask steps.
40. The memory device of claim 38 , wherein the memory includes more than 128 Mbits and the memory devices are formed with fewer than 10 mask steps.
41. A standalone memory device, comprising:
thin-film memory cells arranged in a cross-point array; and
thin-film peripheral circuitry configured to access the thin-film memory cells, wherein the memory includes more than 128 Mbits in a plurality of layers and the memory devices are formed with fewer than 10 mask steps per layer.