Thin-film memory system having thin-film peripheral circuit and memory controller for interfacing with a standalone thin-film memory
View Patent ↗An electronic system includes at least one reduced-complexity integrated circuit memory coupled to a memory controller. By reducing the complexity of each integrated circuit memory and concentrating the complexity within the memory controller, overall system costs may be greatly reduced and reliability improved.
1. An electronic system, comprising:
at least one standalone all thin film memory, including thin-film memory cells arranged in a cross-point array;
thin-film peripheral circuitry configured to access the thin-film memory; and
a thin film memory controller configured to provide access to the at least one standalone all thin film memory, the controller including a system interface circuit, a thin film memory interface circuit, and control circuitry configured to transfer data between the system interface circuit and the thin film memory interface circuit.
2. The electronic system of claim 1 wherein the thin-film peripheral circuitry comprises a thin film address decoder.
3. The electronic system of claim 2 wherein the thin film address decoder comprises three-terminal ovonic threshold switches.
4. The electronic system of claim 3 wherein the thin film address decoder comprises asymmetric-threshold three-terminal ovonic threshold switches.
5. The electronic system of claim 2 , wherein the thin-film peripheral circuitry comprises drivers, the drivers comprising three-terminal ovonic threshold switches.
6. The electronic system of claim 1 wherein the thin-film memory cells comprise phase change devices.
7. The electronic system of claim 6 wherein the thin-film memory cells comprise chalcogenide devices.
8. The electronic system of claim 1 , wherein the peripheral circuitry further comprises four-phase logic circuitry.
9. The electronic system of claim 1 , further comprising:
a microprocessor configured to access the at least one standalone thin film memory.
10. The electronic system of claim 9 further comprising a transmitter/receiver configured to transmit data from and receive data for the microprocessor or standalone thin film memory.
11. The electronic system of claim 10 wherein the memory, microprocessor and transmitter/receiver are configured as a cellular telephone.
12. The electronic system of claim 10 wherein the memory and microprocessor are configured as a handheld entertainment device.
13. The electronic system of claim 1 , wherein the peripheral circuitry includes test registers configured to receive input from an external test device.
14. The electronic system of claim 1 , wherein the peripheral circuitry includes reconfiguration registers configured to receive input from an external test device.
15. The electronic system of claim 1 , wherein the peripheral circuitry includes redundant memory cells configured for mapping into the memory device's memory map under control of an external test device.
16. The electronic system of claim 1 , wherein the memory is configured to receive a reference voltage signal from an external circuitry.
17. The electronic system of claim 1 , wherein the memory is configured to transmit an analog representation of a memory cell value to an external circuitry for conversion to a digital value.
18. The electronic system of claim 1 , further including a substrate upon which the memory cells and peripheral circuitry are formed, the substrate being a non-single crystal material.
19. The electronic system of claim 18 wherein the substrate is a ceramic material.
20. The electronic system of claim 18 wherein the substrate is a fiberglass material.
21. The electronic system of claim 18 wherein the substrate is a glass material.
22. The electronic system of claim 18 wherein the substrate is a quartz material.
23. The electronic system of claim 1 , further comprising:
a memory clock generator configured for distribution to the thin film memory.
24. The electronic system of claim 23 wherein the clock generator is configured to generate a four phase clock.
25. The electronic system of claim 1 , wherein the memory controller further comprises:
an analog interface configured to receive analog signals from the thin film memory;
a sensing circuit configured to sense a value of the received analog signal; and
an encoder circuit configured to encode the sensed value of the received analog signal into a digital value.
26. The electronic system of claim 25 wherein the encoder circuit is configured to encode the sensed analog signal into a n-ary value.
27. The electronic system of claim 25 wherein the encoder circuit is configured to encode the sensed analog signal into a binary value.
28. The electronic system of claim 25 wherein the encoder circuit is configured to encode the sensed analog signal into a ternary value.
29. The electronic system of claim 25 wherein the encoder circuit is configured to encode the sensed analog signal into a quaternary value.
30. The electronic system of claim 25 further comprising refresh circuitry configured to refresh the existing value in a thin film memory cell.
31. The electronic system of claim 30 wherein the refresh circuitry comprises read/rewrite circuitry.