Thin film logic device and system
View Patent ↗Thin film logic circuits employ thin-film switching devices to execute complementary logic functions. Such logic devices operate, as complementary metal oxide semiconductor (CMOS) logic devices do, in a manner that does not provide a direct conduction path between a system supply and a system return. Complementary logic circuits may employ three-terminal threshold switches as switching elements.
1. An apparatus, comprising:
a first three terminal thin film ovonic threshold switching device; and
a second three terminal thin film ovonic threshold switching device, wherein said first and second switching devices are coupled together and configured to perform a logic function.
2. The apparatus of claim 1 wherein the three-terminal thin film ovonic threshold switching devices are asymmetric threshold devices.
3. The apparatus of claim 2 further comprising third and fourth three terminal thin film switching devices, wherein said switching devices are configured as at least one logic gate selected from the group consisting of AND, OR, NOT, NAND, NOR, XOR, and XNOR.
4. The apparatus of claim 2 further comprising a plurality of complementary logic gates configured as a decoder.
5. The apparatus of claim 2 further comprising a plurality of complementary logic gates configured to employ a multi-phase clock.
6. The apparatus of claim 2 further comprising a plurality of complementary logic gates configured as a latch.
7. The apparatus of claim 6 wherein the complementary logic gates are configured to employ a multi-phase clock.
8. The apparatus of claim 2 further comprising a plurality of complementary logic gates configured as a memory controller.
9. The apparatus of claim 8 wherein the complementary logic gates are configured to employ a multi-phase clock.
10. The apparatus of claim 2 further comprising a plurality of complementary logic gates configured as a microprocessor.
11. The apparatus of claim 10 wherein the complementary logic gates are configured to employ a multi-phase clock.
12. An electronic device, comprising:
a logic circuit, including:
a first three terminal thin film ovonic threshold switching device; and
a second three terminal thin film ovonic threshold switching device;
wherein said first and second switching devices are coupled together and configured to perform a logic function; and
a memory array, wherein the logic circuit is configured to interface with the memory array.
13. The electronic device of claim 12 wherein the logic circuit comprises a decoder.
14. The apparatus of claim 12 wherein the logic circuit includes asymmetric-threshold three terminal electronic switching devices.
15. The apparatus of claim 14 wherein the electronic device comprises is a multi-phase clock circuit.
16. The electronic device of claim 14 wherein the logic circuit comprises a latch.
17. The apparatus of claim 16 wherein the logic circuit is a multi-phase clock circuit.
18. The electronic device of claim 12 further comprising a microprocessor configured to interface with the logic circuit.
19. The apparatus of claim 18 wherein the logic circuit includes asymmetric-threshold three terminal electronic switching devices.
20. The apparatus of claim 18 wherein the logic circuit is a multi-phase clock circuit.
21. The electronic device of claim 18 further comprising a transmitter/receiver configured to transmit data from and receive data for the microprocessor or memory.
22. The apparatus of claim 21 wherein the logic circuit includes asymmetric-threshold three terminal electronic switching devices.
23. The apparatus of claim 21 wherein the electronic device comprises is a multi-phase clock circuit.
24. The electronic device of claim 22 wherein the memory, microprocessor and transmitter/receiver are configured as a cellular telephone.
25. The electronic device of claim 18 wherein the memory and microprocessor are configured as a handheld entertainment device.
26. The apparatus of claim 25 wherein the logic circuit includes asymmetric-threshold three terminal electronic switching devices.
27. The apparatus of claim 25 wherein the logic circuit is a multi-phase clock circuit.
28. The electronic device of claim 18 wherein the memory and microprocessor are configured as a solid state drive.
29. The apparatus of claim 28 wherein the logic circuit includes asymmetric-threshold three terminal electronic switching devices.
30. The apparatus of claim 28 wherein the logic circuit is a multi-phase clock circuit.