Memory controller
View Patent ↗A memory controller provides interfaces for one or more thin film memory circuits. The controller may include an analog interface for one or more thin film memories. Such an analog interface may accept analog signals representative of an associated thin film memory's memory state, condition and sense the signal, and encode the signal into a digital value.
1. A memory controller, comprising:
a system interface circuit;
a thin film memory interface circuit;
control circuitry configured to transfer data between the system interface circuit and the thin film memory interface circuit; and
a memory clock generator configured for distribution to thin film memories, the clock generator being configured to generate a four phase clock.
2. A memory controller, comprising:
a system interface circuit;
a thin film memory interface circuit, the thin film memory interface circuit includes circuitry configured to receive analog signals from a thin film memory; and
control circuitry configured to transfer data between the system interface circuit and the thin film memory interface circuit.
3. The memory controller of claim 2 , wherein the thin film memory interface circuit includes circuitry configured to sense a value of the received analog signal.
4. The memory controller of claim 3 , wherein the thin film memory interface circuit includes an encoder circuit configured to encode the sensed value of the received analog signal into a digital value.
5. The memory controller of claim 4 , wherein the encoder circuit is configured to encode the sensed analog signal into a n-ary value.
6. The memory controller of claim 4 , wherein the encoder circuit is configured to encode the sensed analog signal into a binary value.
7. The memory controller of claim 4 , wherein the encoder circuit is configured to encode the sensed analog signal into a ternary value.
8. The memory controller of claim 4 , wherein the encoder circuit is configured to encode the sensed analog signal into a quaternary value.
9. The memory controller of claim 2 , wherein the analog interface is configured to receive a current signal.
10. The memory controller of claim 2 , wherein the analog interface is configured to receive a voltage signal.
11. The memory controller of claim 2 , wherein the interface includes circuitry to condition the received analog signal.
12. The memory controller of claim 2 , further comprising status and control circuitry configured to operate with a thin film memory.
13. The memory controller of claim 12 , wherein the status and control circuitry includes circuitry for indicating to a thin film the n-ary level mode in which it is to operate.
14. The memory controller of claim 2 , further comprising refresh circuitry configured to refresh the existing value in a thin film memory cell.
15. The memory controller of claim 14 , wherein the refresh circuitry comprises read/rewrite circuitry.
16. An apparatus, comprising:
a system interface circuit;
a memory interface circuit including an analog signal input circuit configured to receive analog signal representations of the memory states of memories controlled by the memory controller; and
control circuitry configured to transfer data between the system interface circuit and the thin film memory interface circuit.
17. The apparatus of claim 16 , further comprising control circuitry configured to initiate tests of integrated circuit memories through the memory interface circuit.
18. The apparatus of claim 16 , further comprising control circuitry configured to reconfigure memory based on the results tests initiated by the control circuitry.
19. The apparatus of claim 16 , further comprising:
at least one integrated circuit memory; and
a microprocessor configured to access the at least one standalone thin film memory.
20. The apparatus of claim 19 , further comprising a transmitter/receiver configured to transmit data from and receive data for the microprocessor or standalone thin film memory.
21. The apparatus of claim 20 , wherein the memory, microprocessor and transmitter/receiver are configured as a cellular telephone.
22. The apparatus of claim 20 , wherein the memory and microprocessor are configured as a handheld entertainment device.
23. The apparatus of claim 20 , wherein the memory and microprocessor are configured as a computer.
24. The apparatus of claim 20 , wherein the memory and microprocessor are configured as a solid state drive.