Substrate isolated integrated high voltage diode integrated within a unit cell
View Patent ↗An asymmetric semiconductor device ( 3 ) that includes an integrated high voltage diode ( 72 ), including: a substrate comprising an epitaxial layer ( 47 ) and a deep well implant ( 42 ) of a first type patterned above the epitaxial layer; a shallow trench isolation (STI) region ( 46 ) separating a cathode from an anode; a first well implant ( 40 ) of a second type residing below the anode; and a deep implant mask ( 34 ) of the second type patterned above the deep well implant and below both the cathode and a portion of the STI region.
1. An asymmetric semiconductor device that includes an integrated high voltage diode, comprising:
a deep well implant;
a shallow trench isolation (STI) region separating a cathode from an anode;
a first well implant residing below the anode; and
a deep implant mask patterned above the deep well implant and below both the cathode and a portion of the STI region, wherein the deep implant mask is completely separated from the epitaxial layer by the deep well implant.
2. An asymmetric semiconductor device that includes an integrated high voltage diode, comprising:
a substrate comprising an epitaxial layer and a deep well implant of a first type patterned above the epitaxial layer;
a shallow trench isolation (STI) region separating a cathode from an anode;
a first well implant of a second type residing below the anode; and
a deep implant mask of the second type patterned above the deep well implant and below both the cathode and a portion of the STI region, wherein the deep implant mask is completely separated from the epitaxial layer by the deep well implant.
3. The asymmetric semiconductor device of claim 2 , further comprising a polysilicon wall that resides above the STI region between the cathode and anode, wherein the cathode is separated from an edge of the STI region, and wherein the polysilicon wall is shorted to the cathode.
4. The asymmetric semiconductor device of claim 2 , further comprising a second well implant of the first type that resides next to the first well implant.
5. The asymmetric semiconductor device of claim 4 , wherein the first well implant and the second well implant are separated by a second STI region.
6. The asymmetric semiconductor device of claim 2 , having a surface layout includes a ring-like structure in which a centrally located cathode is surrounded by the STI region, and the STI region is surrounded by the anode.
7. The asymmetric semiconductor device of claim 2 , wherein the STI region has a thickness of 0.35-0.45 μm.
8. The asymmetric semiconductor device of claim 2 , wherein:
the first type comprises an n-type, such that the deep well implant comprises a deep n-type well (DNwell)
the second type comprises a p-type, such that the deep implant mask comprises a deep p-type well (DPWell) and the first well implant comprises a p-type well.
9. The asymmetric semiconductor device of claim 8 , wherein the p-type well is a high voltage p-type well (HPW) comprising a 5 volt retrograde well that is approximately 12.3-15 nm thick.
10. The asymmetric semiconductor device of claim 8 , wherein the p-type well comprises a 2.5 volt retrograde well that is approximately 5.0-5.4 nm thick.
11. The asymmetric semiconductor device of claim 8 , wherein:
the DPWell comprises an implant that is approximately 1-2 MeV 5e12 cm-2 31 Phos for substrate isolation; and
the DPWell comprises an implant that is approximately 500-700 keV 1e13 cm-2 11 B for deep isolation.
12. A method of forming an asymmetric semiconductor device that includes an integrated high voltage diode, comprising:
forming a substrate comprising an epitaxial layer;
forming a deep well implant of a first type above the epitaxial layer;
forming a deep implant mask of a second type above the deep well implant and below a cathode location, wherein the deep implant mask is completely separated from the epitaxial layer by the deep well implant;
forming a first well implant of the second type below an anode location; and
forming a shallow trench isolation (STI) region between the cathode location and the anode location, wherein a portion of the STI region resides above the first well implant of the second type.
13. The method of claim 12 , further comprising the step of forming a polysilicon wall above the STI region between a cathode and an anode, wherein the cathode is separated from an edge of the STI region, and wherein the polysilicon wall is shorted to the cathode.
14. The method of claim 12 , further comprising forming a second well implant of the first type next to the first well implant.
15. The method of claim 14 , wherein the first well implant and the second well implant are separated by a second STI region.
16. The method of claim 12 , wherein the device comprises a surface layout having a ring-like structure in which a centrally located cathode is surrounded by the STI region, and the STI region is surrounded by an anode.
17. The method of claim 12 , wherein the STI region has a thickness of 0.35-0.45 μm.
18. The method of claim 12 , wherein:
the first type comprises an n-type, such that the deep well implant comprises a deep n-type well (DNwell),
the second type comprises a p-type, such that the deep implant mask comprises a deep p-type well (DPWell) and the first well implant comprises a p-type well.
19. The method of claim 18 , wherein the p-type well is a high voltage p-type well (HPW) comprising a 5 volt retrograde well that is approximately 12.3-15 nm thick.
20. The method of claim 18 , wherein:
the p-type well comprises a 2.5 volt retrograde well that is approximately 5.0-5.4 nm thick;
the DPWell comprises an implant that is approximately 1-2 MeV 5e12 cm-2 31 Phos for substrate isolation; and
the DPWell comprises an implant that is approximately 500-700 keV 1e13 cm-2 11 B for deep isolation.