III-nitride power semiconductor device

1. A power semiconductor device, comprising:

a III-nitride heterojunction body that includes a first III-nitride body and a second III-nitride body having a different band gap than that of said first III-nitride body;

a first power electrode comprising a conductive material coupled to said second III-nitride body;

a second power electrode comprising said conductive material coupled to said second III-nitride body;

a gate arrangement including a gate electrode disposed between said first and said second power electrodes; and

a conductive channel that includes a two-dimensional electron gas (2DEG) that in a conductive state includes a reduced charge region produced by an implanted region in said second III-nitride body under said gate electrode, wherein said reduced charge region is less conductive than regions of said 2DEG adjacent each side of said reduced charge region and respectively underlying said first power electrode and said second power electrode without locally eliminating the 2DEG;

said implanted region haying implanted charge in said second III-nitride body, said implanted charge configured to repel electrons in said 2DEG under and beyond edges of said gate electrode;

said reduced charge region extending sufficiently beyond said edges of said gate electrode toward said first and second power electrodes so as to reduce peak electric fields at said edges; and

wherein said first III-nitride body is comprised of a semiconductor alloy from the InAlGaN system, and said second III-nitride body is comprised of another alloy from the InAlGaN system.

2. A power semiconductor device, comprising:

a III-nitride heterojunction body that includes a first III-nitride body and a second III-nitride body having a different band gap than that of said first III-nitride body;

a first power electrode comprising a conductive material coupled to said second III-nitride body;

a second power electrode comprising said conductive material coupled to said second III-nitride body;

a gate arrangement including a gate electrode disposed between said first and said second power electrodes; and

a conductive channel that includes a two-dimensional electron gas (2DEG) that in a conductive state includes a reduced charge region produced by an implanted region in said second III-nitride body under said gate electrode, wherein said reduced charge region is less conductive than regions of said 2DEG adjacent each side of said reduced charge region and respectively underlying said first power electrode and said second power electrode without locally eliminating the 2DEG;

said implanted region haying implanted charge in said second III-nitride body, said implanted charge configured to repel electrons in said 2DEG under and beyond first and second edges of said gate electrode;

said reduced charge region extending sufficiently beyond said first and second edges of said gate electrode so as to reduce peak electric fields at each of said first and second edges; and

wherein said first III-nitride body is comprised of a semiconductor alloy from the InAlGaN system, and said second III-nitride body is comprised of another alloy from the InAlGaN system.

3. The power semiconductor device of claim 2 , wherein said gate arrangement includes a gate insulation body.

4. The power semiconductor device of claim 2 , wherein said gate arrangement does not include a field plate.

5. The power semiconductor device of claim 2 , further comprising a passivation body disposed over said III-nitride heterojunction body.

6. The semiconductor device of claim 2 , wherein said first III-nitride body is comprised of GaN and said second III-nitride body is comprised of AlGaN.

7. The semiconductor device of claim 2 , wherein said heterojunction body is disposed over a substrate.

8. The semiconductor device of claim 7 , wherein said substrate is comprised of silicon.

9. The semiconductor device of claim 7 , wherein said substrate is comprised of silicon carbide.

10. The semiconductor device of claim 7 , wherein said substrate is comprised of sapphire.

11. The semiconductor device of claim 7 , wherein said substrate is comprised of a III-nitride material.

12. The semiconductor device of claim 11 , wherein said III-nitride material is GaN.

13. The semiconductor device of claim 7 , further comprising a transition body disposed between said substrate and said III-nitride heterojunction body.

14. The semiconductor device of claim 13 , wherein said transition body is comprised of a III-nitride material.

15. The semiconductor device of claim 14 , wherein said transition body is comprised of AlN.