IP Library Granted Patent US 7,773,010
Granted Patent B2
US 7,773,010 · App. 12/162,814 · Granted Aug 10, 2010

A/D converter comprising a voltage comparator device

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Quick Facts
Patent No.
US 7,773,010
App. No.
12/162,814
Granted
Aug 10, 2010
Kind
B2
Abstract

The present invention is related to an analogue-to-digital (A/D) converter comprising at least two voltage comparator devices. Each of the voltage comparator devices is arranged for being fed with a same input signal and for generating an own internal voltage reference. The two internal voltage references are different. Each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal.

Claims (19)

1. An analogue-to-digital (A/D) converter comprising at least two voltage comparator devices, each of said voltage comparator devices comprising a plurality of transistors, arranged for being fed with a same input signal and for generating an own internal voltage reference, wherein each said voltage reference is realized by configuring at least one of said transistors such that a voltage imbalance is achieved between the output signals of said voltage comparator devices, wherein said internal voltage references are different, and whereby each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal.

2. The A/D converter as in claim 1 , wherein at least one of said voltage comparator devices further comprises capacitors for calibrating transistor mismatches.

3. The A/D converter as in claim 2 , wherein said capacitors are switchable.

4. The A/D converter as in claim 2 , wherein at least one of said capacitors have a capacitance value of a capacitance of half MOS transistors.

5. The A/D converter as in claim 2 , wherein at least one of said capacitors are configured in a differential structure.

6. The A/D converter as in claim 2 , further comprising a memory device for storing calibration information for selecting said capacitors for calibrating transistor mismatches.

7. The A/D converter as in claim 1 , wherein at least one of said voltage comparator devices further comprises capacitors for calibrating transistor mismatches.

8. The A/D converter as in claim 2 , wherein at least one of said capacitors have a capacitance value of a capacitance of half MOS transistors.

9. The A/D converter as in claim 3 , wherein at least one of said capacitors are configured in a differential structure.

10. The A/D converter as in claim 4 , wherein at least one of said capacitors are configured in a differential structure.

11. The A/D converter as in claim 3 , further comprising a memory device for storing calibration information for selecting said capacitors for calibrating transistor mismatches.

12. The A/D converter as in claim 4 , further comprising a memory device for storing calibration information for selecting said capacitors for calibrating transistor mismatches.

13. The A/D converter as in claim 5 , further comprising a memory device for storing calibration information for selecting said capacitors for calibrating transistor mismatches.

14. An ultra-wide band receiver comprising an analogue-to-digital (A/D) converter,

wherein the A/D converter comprises at least two voltage comparator devices, each of said voltage comparator devices comprising a plurality of transistors and arranged for being fed with a same input signal and for generating an own internal voltage reference, each of said internal voltage references being different and realized by configuring at least some of said transistors such that a voltage imbalance is achieved between the output signals of said voltage comparator devices,

wherein each voltage comparator is arranged for generating an output signal indicative of a bit position of a digital approximation of said input signal.

15. The ultra-wide band receiver as in claim 14 , wherein at least one of said voltage comparator devices further comprises capacitors for calibrating transistor mismatches.

16. The ultra-wide band receiver as in claim 15 , wherein least one of said capacitors are configured in a differential structure.

17. The ultra-wide band receiver as in claim 15 , wherein the A/D converter further comprises a memory device for storing calibration information for selecting said capacitors for calibrating transistor mismatches.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2009
From: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM
To: IMEC
Reel/Frame 023419/0185 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 4, 2008
From: VAN DER PLAS, GEERT; NUZZO, PIERLUIGI; DE BERNARDINIS, FERNANDO
To: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM
Reel/Frame 021783/0059 →