Method for constructing a variable bitwidth video processor

1. A method for designing a video processor with a variable and programmable bitwidth parameter, comprising:

selecting logical operations having propagation delay that scales substantially linearly with the bitwidth, wherein the bitwidth is variable;

determining a desired tradeoff curve that defines a plurality of bitwidths and a plurality of pixel clock frequencies in which the video processor should function;

grouping instances of a logic operation having same properties;

for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation;

applying, by a computer, matching parameters computed for a single instance to all instances in a group of instances; and

outputting a design of the video processor.

2. The method of claim 1 , wherein the plurality of bitwidths and the plurality of pixel clock frequencies are determined according to an application for which the video processor is being utilized.

3. The method of claim 2 , wherein the pixel clock frequencies requirements are verified by static timing analysis, providing different sets of timing constraints for different bitwidths.

4. The method of claim 1 , wherein matching the propagation delay and bitwidth of the logic operation to meet the desired tradeoff further comprising:

determining if the logic operation is a critical operation;

tuning the actual curve of critical operations to meet the desired curve; and

optimizing non-critical logic operations.

5. The method of claim 4 , wherein the critical operation is a logic operation having a slack higher than a predefined threshold or a negative slack.

6. The method of claim 4 , wherein tuning the actual curve of critical operations further comprising:

inserting a pipeline when an offset of the actual curve is larger than the offset of the desired curve; and

performing a uniform gate sizing to match the slopes of the actual curve and the desired curve.

7. The method of claim 4 , further comprising:

when the actual curve and the desired curve cannot be matched,

partitioning the bitwidth of the logic operation to a group of bits including an effective bitwidth that matches the desired curve and a group of an extra bitwidth; and

removing the bits in the extra bitwidth group from the logic operation.

8. The method of claim 4 , wherein optimizing the non-critical logic operations further comprising: changing properties of logic gates performing the logic operations, wherein the properties include at least one of: a gate size and power consumption of a gate.

9. A non-transitory computer-readable medium having stored thereon computer executable code for performing for designing a video processor with a variable and programmable bitwidth parameter, comprising:

selecting logical operations having propagation delay that scales substantially linearly with the bitwidth, wherein the bitwidth is variable;

determining a desired tradeoff curve that defines a plurality of bitwidths and a plurality of pixel clock frequencies in which the video processor should function;

grouping instances of a logic operation having same properties;

for a single instance of each logic operation, matching an actual curve of the logic operation to the desired tradeoff curve, wherein the actual curve is determined by the propagation delay and bitwidth of the logic operation;

applying matching parameters computed for a single instance to all instances in a group of instances; and

outputting a design of the video processor.

10. The non-transitory computer-readable medium of claim 9 , wherein the plurality of bitwidths and the plurality of pixel clock frequencies are determined set of frequencies required by the application for which the video processor is being utilized.

11. The non-transitory computer-readable medium of claim 10 , wherein the pixel clock frequencies requirements are verified by a static timing analysis tool, thereby providing different sets of timing constraints for different bitwidths.

12. The non-transitory computer-readable medium of claim 9 , wherein matching the propagation delay and bitwidth of the logic operation to meet the desired tradeoff further comprising:

determining if the logic operation is a critical operation;

tuning the actual curve of critical operations to meet the desired curve; and

optimizing non-critical logic operations.

13. The non-transitory computer-readable medium of claim 12 , wherein a critical operation is a logic operation having a slack higher than a predefined threshold or a negative slack.

14. The non-transitory computer-readable medium of claim 12 , wherein tuning the actual curve of critical operations further comprising:

inserting a pipeline when an offset of the actual curve is larger than the offset of the desired curve; and

performing a uniform gate sizing to match the slopes of the actual curve and the desired curve.

15. The non-transitory computer-readable medium of claim 12 , further comprising:

when the actual curve and the desired curve cannot be matched,

partitioning the bitwidth of the logic operation to a group of bits including an effective bitwidth that matches the desired curve and a group of an extra bitwidth; and

removing the bits in the extra bitwidth group from the logic operation.

16. The non-transitory computer-readable medium of claim 12 , wherein optimizing the non-critical logic operations further comprising: changing properties of logic gates performing the logic operations, wherein the properties include at least one of: a gate size and power consumption of a gate.