Method for fabricating tungsten line and method for fabricating gate of semiconductor device using the same

1. A method for fabricating a tungsten (W) line, the method consisting of:

forming a silicon-containing layer over a substrate;

forming a diffusion barrier layer over the silicon-containing layer;

forming a tungsten layer over the diffusion barrier layer;

performing a thermal treatment process on the substrate including the tungsten layer to increase a grain size of the tungsten layer; and

forming a hard mask layer over the tungsten layer having the increased grain size,

wherein the thermal treatment process is performed before the hard mask layer is formed over the tungsten layer, and the thermal treatment process is performed in a hydrogen (H 2 ) atmosphere.

2. The method as recited in claim 1 , wherein the thermal treatment process is a rapid thermal treatment process (RTP).

3. The method as recited in claim 2 , wherein the thermal treatment process is performed at a temperature of approximately 800° C. to approximately 1,000° C.

4. The method as recited in claim 1 , wherein the tungsten layer is formed using a physical vapor deposition (PVD) method.

5. The method as recited in claim 1 , wherein the diffusion barrier layer has a crystal-like structure.

6. The method as recited in claim 5 , wherein the diffusion barrier layer has a crystalline structure.

7. The method as recited in claim 1 , wherein the diffusion barrier layer has a stack structure of a titanium (Ti) layer and a tungsten nitride (WN) layer.

8. The method as recited in claim 1 , wherein the diffusion barrier layer is a stack structure of TiN/WN or a stack structure of Ti/TiN/WN.

9. The method as recited in claim 1 , wherein the diffusion barrier layer includes a stack structure of a first layer including titanium and a second layer including tungsten, and the diffusion barrier layer has a crystal-like structure.

10. The method as recited in claim 1 , wherein the silicon-containing layer includes a polysilicon layer.

11. The method as recited in claim 10 , wherein the polysilicon layer includes impurities.

12. The method as recited in claim 11 , wherein the impurities include boron (B), arsenic (As), phosphorus (P), or a combination thereof.

13. The method as recited in claim 1 , wherein a stack structure of the silicon-containing layer, the diffusion barrier layer and the thermal treated tungsten layer defines a gate, a bit line, or a metal line.

14. The method as recited in claim 1 , wherein the hard mask layer includes a nitride layer.

15. A method for fabricating a gate of a semiconductor gate, the method consisting of:

forming a gate insulation layer over a substrate;

forming a silicon-containing layer over the gate insulation layer;

forming a diffusion barrier layer over the silicon-containing layer, the diffusion barrier layer having a crystal-like structure;

forming a tungsten layer over the diffusion barrier layer, the tungsten layer having a crystal-like structure and a first average grain size;

performing a thermal treatment process on the substrate including the tungsten layer, the tungsten layer having a second average grain size after the thermal treatment, the second average grain size being larger than the first average grain size; and

forming a gate hard mask layer over the tungsten layer having the second average grain size,

wherein the thermal treatment process is performed before the gate hard mask layer is formed over the tungsten layer, and the thermal treatment process is performed only in a hydrogen (H 2 ) atmosphere.

16. The method as recited in claim 15 , wherein the thermal treatment process is a rapid thermal treatment process (RTP).

17. The method as recited in claim 16 , wherein the thermal treatment process is performed at a temperature of approximately 800° C. to approximately 1,000° C.

18. The method as recited in claim 15 , wherein the tungsten layer is formed using a physical vapor deposition (PVD) method.

19. The method as recited in claim 15 , wherein the diffusion barrier layer has a stack structure of a TiN layer and a WN layer, wherein each of the TiN layer and the WN layer has a crystalline structure.

20. The method as recited in claim 15 , wherein the diffusion barrier layer includes a stack structure of TiN/WN layers or a stack structure of Ti/TiN/WN layers.

21. The method as recited in claim 15 , wherein the diffusion barrier layer is formed using a PVD method.

22. The method as recited in claim 15 , wherein the silicon-containing layer includes a polysilicon layer.

23. The method as recited in claim 22 , wherein the polysilicon layer includes impurities, the impurities including boron (B), arsenic (As), or phosphorus (P), or a combination thereof.

24. The method as recited in claim 15 , wherein the silicon-containing layer is a polysilicon layer including a first region having P-type impurities and a second region having N-type impurities.