Non-volatile semiconductor memory device adapted to store a multi-valued data in a single memory cell

1. A non-volatile semiconductor memory device comprising:

a plurality of electrically data rewritable non-volatile semiconductor memory cells;

a memory cell array in which the plurality of memory cells or memory cell units are arranged in matrix, the memory cell unit including at least one of the memory cells;

a plurality of word lines connected to gates of the memory cells;

a write circuit configured to write data in a plurality of selected memory cells in the memory cells, the plurality of selected memory cells being connected to a selected word line, the write circuit writing a data in the plurality of selected memory cells by supplying a write voltage to the selected word line; and

a write verify circuit configured to perform write verify operation for the plurality of selected memory cells by supplying a first write verify voltage and a second write verify voltage to the selected word line;

wherein write step operations and write verify operations are repeated when writing data into the plurality of selected memory cells, the write voltage is supplied to the selected word line in each of the write step operations, a first step write verify operation and a second step write verify operation are performed between (n-th) write step operation and (n+1-th) write step operation (where n is a natural number), the first write verify voltage and the second write verify voltage are respectively supplied to the selected word line in the first step write verify operation and the second step write verify operation, the first write verify voltage and the second write verify voltage are different from each other; and

wherein there are plurality of distributions of threshold value of the memory cells, the plurality of distributions of threshold value includes a first distribution of threshold value and a second distribution of threshold value, the second distribution of threshold value has higher threshold values than the first distribution of threshold value, there is no distribution of threshold value between the first distribution of threshold value and the second distribution of threshold value, both the first write verify voltage and the second write verify voltage are higher than a center value of the first distribution of threshold value, both the first write verify voltage and the second write verify voltage are lower than a center value of the second distribution of threshold value, and the write voltage increases with a stepwise increment of predetermined voltage as the write step operation is repeated.

2. The device according to claim 1 , wherein at least a part of the plurality of memory cells is capable of storing data more than 1 bit.

3. The device according to claim 1 , wherein at least a part of the plurality of memory cells is capable of storing more than two-valued data.

4. The device according to claim 1 , wherein there are at least four distributions of threshold value of the memory cells.

5. The device according to claim 1 , further comprising:

a first selection gate;

a first selection gate line being connected to the first selection gate;

a second selection gate; and

a second selection gate line being connected to the second selection gate,

wherein the memory cell unit includes serially connected memory cells, the first selection gate is connected between a bit line and one end of the serially connected memory cells, and second selection gate is connected between a source line and the other end of the serially connected memory cells.

6. The device according to claim 1 , wherein the write circuit configured to write data in the plurality of selected memory cells in the memory cells, the write circuit writes a data in the plurality of selected memory cells by supplying a write control voltage to the plurality of selected memory cells, and the write control voltage is different from the write voltage.

7. The device according to claim 6 , further comprising:

a first memory cell included in the memory cells;

a second memory cell included in the memory cells; and

a third memory cell included in the memory cells, gates of the first memory cell, the second memory cell and the third memory cells being connected to a first word line,

wherein a first write control voltage, a second write control voltage and a third write control voltage are respectively supplied to the first memory cell, the second memory cell and the third memory cell while at least one write step operation is performed for a first word line, all of the first memory cell, the second memory cell and the third memory cell are included in the second distribution of threshold value after completion of writing data in memory cells connected to the first word line, and the first write control voltage, the second write control voltage and the third write control voltage are different one another.

8. The device according to claim 5 , wherein the write verify circuit is configured to keep potentials of the first and second selection gate lines at values higher than 0V, for time from ending of the first step write verify operation to beginning of the second step write verify operation.

9. The device according to claim 5 , wherein the write verify circuit is configured to set at least one of potentials of the first and second gate lines to 0V in at least a time period of time from ending of the first step write verify operation to beginning of the second step write verify operation.

10. The device according to claim 9 , wherein the write verify circuit is configured to set both potentials of the first and second selection gate lines to 0V in at least a time period of time from ending of the first step write verify operation to beginning of the second step write verify operation.

11. The device according to claim 1 , wherein the write verify circuit is configured so as not to perform a charging operation for a bit line for time from ending of the first step write verify operation to ending of the second step write verifying operation.

12. The device according to claim 11 , wherein the write verifying circuit is configured to perform a charging operation for the bit line only once for time from beginning of the first step write verify operation to ending of the second step write verify operation.

13. The device according to claim 6 , further comprising:

a plurality of bit lines connected to gates of the memory cells,

wherein the first write control voltage, the second write control voltage and the third write control voltage are respectively supplied to the first memory cell through corresponding bit lines.

14. The device according to claim 1 , wherein the first distribution of threshold value is distribution of the lowest threshold value and corresponds to a negative threshold value being lower than 0V.

15. The device according to claim 1 , wherein the second distribution of threshold value is neither distribution of the lowest threshold value nor distribution of the highest threshold value.

16. The device according to claim 1 , wherein at least a part of the plurality of memory cells is capable of storing at least two bits, and the at least two bits belong respectively to different row address or different pages.

17. The device according to claim 7 , wherein the first write control voltage is lower than the second write control voltage, and the second write control voltage is lower than the third write control voltage, at least a part of the plurality of memory cells is capable of storing at least two bits and stores a data in both a first row address and a second row address which corresponds to higher address than the first row address, the second write control voltage is supplied to the memory cells when the write circuit writes a data in the second row address in the memory cells, and the second write control voltage is not supplied to the memory cells when the write circuit writes a data in the first row address in the memory cells.

18. The device according to claim 1 , wherein the memory cell units are arranged in matrix in the memory cell array, and the plurality of memory cells are connected in series in the memory cell unit.