Semiconductor device and method of controlling the same
View Patent ↗A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.
1. A semiconductor device comprising:
a plurality of digit line pairs connected to a memory cell;
a common signal line pair connected to the plurality of digit line pairs in common;
a common signal line equalizer performing precharge of the common signal line pair; and
a control circuit starting the precharge of the common signal line pair irrespective of a signal level of a mask signal received from an outside, and determining whether the precharge is continued based on the mask signal during the precharge of the common signal line pair.
2. The semiconductor device according to claim 1 , wherein the control circuit includes a common signal line precharge signal generating circuit generating a common signal line precharge signal controlling the common signal line equalizer by setting a pulse width of a pulse signal generated by a pulse generator in accordance with the signal level of the mask signal.
3. The semiconductor device according to claim 1 , further comprising a write amplifier driving write data in the common signal line pair, wherein
the control circuit includes a write amplifier control signal generating circuit generating a write amplifier control signal controlling the write amplifier by setting a pulse width of a pulse signal generated by a pulse generator in accordance with a signal level of a write amplifier enable signal received from an outside.
4. The semiconductor device according to claim 1 , wherein the semiconductor device is a DRAM performing a burst operation.
5. A method of controlling a semiconductor device comprising a plurality of digit line pairs connected to a memory cell, a common signal line pair connected to the plurality of digit line pairs in common, and a common signal line equalizer performing precharge of the common signal line pair, the method comprising:
starting the precharge of the common signal line pair connected to a digit line pair in common irrespective of a signal level of a mask signal received from an outside; and
determining whether the precharge is continued based on the mask signal during the precharge of the common signal line pair.
6. The method of controlling the semiconductor device according to claim 5 , wherein it is determined whether the precharge of the common signal line pair is continued or not based on an internal mask signal, whose a pulse width is set in accordance with the signal level of the mask signal.
7. The method of controlling the semiconductor device according to claim 5 , wherein the precharge is started with a trigger of completion of writing of the digit line.
8. The method of controlling the semiconductor device according to claim 5 , wherein the semiconductor device is a DRAM performing a burst operation.