Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein

1. A shielded gate trench field effect transistor (FET), comprising:

trenches extending into a semiconductor region;

a shield electrode in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

a gate electrode over the shield electrode; and

an inter-electrode dielectric (IED) extending between the shield electrode and the gate electrode, the IED comprising an insulating material comprising undoped oxide in a central portion of the IED and a low-k dielectric extending along sides and bottom of the insulating material.

2. The shielded gate trench FET of claim 1 wherein the IED comprises a high-k dielectric, the high-k dielectric extending between the low-k dielectric and the gate electrode.

3. The shielded gate trench FET of claim 1 wherein the gate electrode comprises metal.

4. The shielded gate trench FET of claim 1 further comprising:

a conductive liner extending between the gate electrode and the semiconductor region.

5. The shielded gate trench FET of claim 1 wherein the semiconductor region further comprises:

a drift region of a first conductivity type extending over a substrate, the substrate having a higher doping concentration than the drift region;

a body region of a second conductivity type extending over the drift region; and

source regions of the first conductivity type adjacent to each trench in the body region, wherein the trenches extend into and terminate within the substrate.

6. The shielded gate trench FET of claim 1 wherein the semiconductor region comprises:

a drift region of a first conductivity type extending over a substrate, the substrate having a higher doping concentration than the drift region;

a body region of a second conductivity type extending over the drift region; and

source regions of the first conductivity type adjacent to each trench in the body region, wherein the trenches extend into and terminate within the drift region.

7. The shielded gate trench FET of claim 6 wherein top surfaces of the IED are recessed relative to the body region.

8. The shielded gate trench FET of claim 6 further comprising:

an interconnect layer extending over the semiconductor region, the interconnect layer contacting the source regions and being isolated from the gate electrode by a dielectric cap; and

a dielectric liner comprising nitride extending between the dielectric cap and the gate electrode.

9. The shielded gate trench FET of claim 1 including a gate dielectric lining upper trench sidewalls, the gate dielectric comprising a high-k dielectric.

10. The shielded gate trench FET of claim 9 wherein the high-k dielectric comprises oxide, and a concentration of the oxide is graded along a thickness of the high-k dielectric, the concentration of the oxide being highest in a portion of the high-k dielectric nearest the semiconductor region.

11. The shielded gate trench FET of claim 9 wherein the high-k dielectric extends along a bottom of the gate electrode.

12. The shielded gate trench FET of claim 9 wherein a physical thickness of the IED is less than the physical thickness of the gate dielectric.

13. The shielded gate trench FET of claim 9 wherein the gate dielectric further comprises thermal oxide.

14. A shielded gate trench field effect transistor (FET), comprising:

trenches extending into a semiconductor region;

a shield electrode in a bottom portion of each trench;

a gate electrode over the shield electrode;

an inter-electrode dielectric (IED) extending between the shield electrode and the gate electrode, the IED comprising a low-k dielectric and an oxide region, the low-k dielectric extending along each side and a bottom of the oxide region; and

a gate dielectric extending between the gate electrode and the semiconductor region, the gate dielectric comprising a high-k dielectric.

15. The shielded gate trench FET of claim 14 wherein the high-k dielectric comprises oxide, and a concentration of the oxide is graded along a thickness of the high-k dielectric, the concentration of the oxide being highest in a portion of the high-k dielectric nearest the semiconductor region.

16. The shielded gate trench FET of claim 14 wherein the high-k dielectric extends along a bottom of the gate electrode.

17. The shielded gate trench FET of claim 14 further comprising:

a gate dielectric lining upper trench sidewalls; and

a conductive liner extending between the gate electrode and the gate dielectric.

18. The shielded gate trench FET of claim 14 wherein the gate electrode comprises metal.

19. A shielded gate trench field effect transistor (FET), comprising:

trenches extending into a semiconductor region;

a shield electrode in a bottom portion of each trench, the shield electrode being insulated from the semiconductor region by a shield dielectric;

a gate electrode over the shield electrode;

a conductive liner extending between the gate electrode and the semiconductor region; and

an inter-electrode dielectric (IED) extending between the shield electrode and the gate electrode, the IED comprising a low-k dielectric.

20. The shielded gate trench FET of claim 19 wherein the IED comprises a high-k dielectric, the high-k dielectric extending between the low-k dielectric and the gate electrode.

21. The shielded gate trench FET of claim 19 wherein the gate electrode comprises metal.

22. The shielded gate trench FET of claim 19 wherein the semiconductor region further comprises:

a drift region of a first conductivity type extending over a substrate, the substrate having a higher doping concentration than the drift region;

a body region of a second conductivity type extending over the drift region; and

source regions of the first conductivity type adjacent to each trench in the body region.

23. The shielded gate trench FET of claim 19 including a gate dielectric lining upper trench sidewalls and extending between the conductive liner and the semiconductor region, the gate dielectric comprising a high-k dielectric.