Light emitting diode and method for manufacturing the same
View Patent ↗A light emitting diode includes a current leakage passage electrically connected in parallel to an active layer to better protect the light emitting diode from static electricity. The light emitting diode includes a substrate, an n-type nitride semiconductor layer on the substrate, an active layer on the n-type nitride semiconductor layer, a p-type semiconductor layer on the active layer, a p-electrode on the p-type semiconductor layer, and an n-electrode formed from the n-type semiconductor layer, exposed by etching, to a portion of the p-type semiconductor layer.
1. A light emitting diode, comprising:
an n-type nitride semiconductor layer;
an active layer arranged on the n-type nitride semiconductor layer;
a p-type semiconductor layer arranged on the active layer;
a p-electrode arranged on the p-type semiconductor layer; and
an n-electrode arranged on an exposed portion of the n-type semiconductor layer and arranged on a portion of the p-type semiconductor layer,
wherein the entire n-electrode comprises a conductive material, and
wherein the n-electrode directly contacts an upper surface and a side surface of the p-type semiconductor layer.
2. The light emitting diode according to claim 1 , wherein the exposed portion of the n-type semiconductor layer and the p-type semiconductor layer include an inclined etching surface and the active layer is exposed to the inclined etching surface.
3. The light emitting diode according to claim 1 , wherein the exposed portion of the n-type semiconductor layer, the portion of the p-type semiconductor layer, or both are subjected to plasma treatment to change electrical characteristics.
4. The light emitting diode according to claim 3 , wherein the plasma treatment is performed using a gas comprising N, NO, NH, He, Ne, Ar, or a combination thereof.
5. The light emitting diode according to claim 3 , wherein the electrical characteristics of the semiconductor layer or semiconductor layers subjected to the plasma treatment are varied according to applied power of the plasma treatment.
6. The light emitting diode according to claim 3 , wherein the electrical characteristics of the semiconductor layer or semiconductor layers subjected to the plasma treatment are varied according to treatment duration of the plasma treatment.
7. The light emitting diode according to claim 3 , wherein the electrical characteristics of the semiconductor layer or semiconductor layers subjected to the plasma treatment are varied according to treatment duration and applied power of the plasma treatment.
8. The light emitting diode according to claim 3 , further comprising:
a reflective plate arranged on the p-electrode,
wherein the reflective plate and the n-electrode are attached to a sub-mount to constitute the light emitting diode as a flip chip type light emitting diode.
9. The light emitting diode according to claim 1 , further comprising an insulation film arranged on the exposed portion of the n-type semiconductor layer, an inclined surface including the active layer, and the portion of the p-type semiconductor layer.
10. The light emitting diode according to claim 1 , wherein the n-type semiconductor layer, the active layer, and the p-type semiconductor layer each comprise nitride-based semiconductor materials.
11. The light emitting diode according to claim 1 , wherein the n-electrode comprises Ti, Al, Pt, Pd, Au, Cr, Fe, Cu, Mo, or a combination thereof.
12. The light emitting diode according to claim 1 , wherein the n-electrode comprises a current passage connected in parallel to the active layer.
13. The light emitting diode according to claim 1 , wherein contact resistance between the n-electrode and the semiconductor layers are determined by contact areas between the n-electrode and the semiconductor layers.
14. The light emitting diode according to claim 1 , wherein the upper surface of the p-type semiconductor layer is continuous.
15. The light emitting diode according to claim 14 , wherein the p-electrode and the n-electrode are both arranged on the continuous upper surface of the p-type semiconductor.