IP Library Granted Patent US 7,776,679
Granted Patent B2
US 7,776,679 · App. 12/175,877 · Granted Aug 17, 2010

Method for forming silicon wells of different crystallographic orientations

Assignees: STMicroelectronics Crolles 2 SAS; STMicroelectronics S.A.
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Quick Facts
Patent No.
US 7,776,679
App. No.
12/175,877
Granted
Aug 17, 2010
Kind
B2
Abstract

A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

Claims (31)

1. A method for manufacturing silicon wells of two crystallographic orientations and having smooth upper surfaces, in a silicon support, comprising the successive steps of:

forming a silicon layer having a first crystallographic orientation on a silicon substrate having a second crystallographic orientation;

forming insulating walls which extend at least down to a border between the silicon substrate and the silicon layer, the insulating walls defining wells;

performing, in at least one well, a chemical vapor etch of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and

performing, in the at least one well, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer, this epitaxy being performed in said epitaxy reactor.

2. The method of claim 1 , wherein the etch and epitaxy steps are carried out at a pressure ranging between 600 Pa and 11,000 Pa.

3. The method of claim 1 , wherein the first crystallographic orientation has a (110) orientation and the second crystallographic orientation has a (100) orientation.

4. The method of claim 1 , wherein the silicon precursor belongs to the group consisting essentially of trichlorosilane, dichlorosilane, and silicon hydrides.

5. The method of claim 1 , wherein performing, in at least one well, a chemical vapor etch of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C. comprises performing in the at least one well, a chemical vapor etch of the silicon layer by means of hydrochloric acid, in the epitaxy reactor, at a temperature ranging between 700° C. and 900° C.

6. A method for manufacturing silicon wells of two crystallographic orientations and having smooth upper surfaces, in a silicon support, the method comprising:

forming a silicon layer having a first crystallographic orientation on a silicon substrate;

forming insulating walls which extend at least down to a border between the silicon substrate and the silicon layer, the insulating walls defining wells;

etching a portion of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and

performing, in at least one well, a vapor-phase epitaxy on the silicon substrate at a temperature ranging between 700° C. and 900° C., this epitaxy being performed in said epitaxy reactor.

7. A method for manufacturing silicon wells of two crystallographic orientations in a silicon support, the method comprising:

forming a silicon layer having a first crystallographic orientation on a silicon substrate;

forming insulating walls that extend at least down to a border between the silicon substrate and the silicon layer;

in an epitaxy reactor:

etching at least one well in the silicon layer; and

epitaxially growing silicon in the at least one well such that an upper surface of a resulting epitaxy layer remains planar.

8. The method of claim 7 , further comprising passivating insulating wall surfaces so that growth is only performed from a surface of the silicon substrate.

9. The method of claim 8 , wherein passivating the insulating wall surfaces comprises flowing hydrochloric acid during epitaxy growth.

10. The method of claim 9 , further comprising flowing one of Silicon hydride, trichlorosilane, and dichlorosilane during epitaxy growth.

11. The method of claim 10 , wherein flowing one of silicon hydride, trichlorosilane and dichlorosilane comprises flowing silicon hydride, trichlorosilane and dichlorosilane at a temperature ranging between 700° C. and 900° C.

12. The method of claim 8 , further comprising flowing one of silicon hydride, trichlorosilane, and dichlorosilane during epitaxy growth.

13. The method of claim 12 , wherein flowing one of silicon hydride, trichlorosilane and dichlorosilane comprises flowing silicon hydride, trichlorosilane and dichlorosilane at a temperature ranging between 700° C. and 900° C.

14. The method of claim 7 , wherein after epitaxy growth, a first well comprises silicon of the first crystallographic orientation and a second well comprises a second crystallographic orientation.

15. The method of claim 7 , wherein etching comprises performing a chemical vapor etch using hydrochloric acid with hydrogen being used as a carrier gas.

16. The method of claim 15 , wherein etching is performed at a temperature ranging between 700° C. and 950° C.

17. The method of claim 16 , wherein etching is performed at a pressure ranging between 600 Pa and 11,000 Pa.

18. The method of claim 7 , wherein etching comprises etching in a manner to avoid etching insulating walls to maintain a planar character of the walls.

Assignments (3)
CHANGE OF NAME Recorded Jan 21, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066357/0612 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT AN ERROR IN THE COVER SHEET PREVIOUSLY RECORDED PREVIOUSLY RECORDED ON REEL 021259 FRAME 0077. ASSIGNOR(S) HEREBY CONFIRMS THE TO ADD AN ASSIGNEE THAT WAS INADVERTENTLY OMITTED FROM THE COVER SHEET BUT INCLUDED IN THE ASSIGNMENT. Recorded Aug 13, 2008
From: LOUBET, NICOLAS; DUTARTRE, DIDIER; BOEUF, FREDERIC
To: STMICROELECTRONICS CROLLES 2 SAS; STMICROELECTRONICS S.A.
Reel/Frame 021378/0043 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2008
From: LOUBET, NICOLAS; DUTARTRE, DIDIER; BOEUF, FREDERIC
To: STMICROELECTRONICS CROLLES 2 SAS
Reel/Frame 021259/0077 →
Priority Claims (1)
FR 07 56652 · Jul 20, 2007 · national
Continuity (1)
Related Publication 20090023275A1 · Jan 22, 2009