A-D convert apparatus

1. A successive approximation AD conversion apparatus that outputs digital output data corresponding to an analog input signal, comprising:

a bit selecting section that selects a conversion target bit sequentially from a highest bit of the output data;

a data control section that outputs comparison data determining a value of the conversion target bit, each time a conversion target bit is selected;

a DA converting section that outputs an analog comparison signal corresponding to the comparison data;

a comparing section that outputs a comparison result between the input signal and the comparison signal, upon the output of the comparison signal by the DA converting section, and that is reset after outputting the comparison result;

a completion detecting section that, upon detecting that the comparing section has output the comparison result, outputs a completion signal causing the bit selecting section to select a next conversion target bit, prior to the comparing section being reset; and

an output section that outputs output data in which a value of each bit is based on the comparison result by the comparing section.

2. A successive approximation AD conversion apparatus that outputs digital output data corresponding to an analog input signal, comprising:

a bit selecting section that selects a conversion target bit sequentially from a highest bit of the output data;

a data control section that outputs comparison data determining a value of the conversion target bit, each time a conversion target bit is selected;

a DA converting section that outputs an analog comparison signal corresponding to the comparison data;

a comparing section that outputs a comparison result between the input signal and the comparison signal, upon the output of the comparison signal by the DA converting section, and that is reset after outputting the comparison result;

a completion detecting section that, upon detecting that the comparing section has output the comparison result, outputs a completion signal causing the bit selecting section to select a next conversion target bit, prior to the comparing section being reset; and

an output section that outputs output data in which a value of each bit is based on the comparison result by the comparing section, wherein

the data control section outputs the comparison data indicating a boundary between (i) output data in which the conversion target bit is equal to zero and bits higher than the conversion target bit have values based on the comparison result and (ii) output data in which the conversion target bit is equal to one and the bits higher than the conversion target bit have values based on the comparison result.

3. The AD conversion apparatus according to claim 2 , further comprising

a timing generating section that generates a comparison control signal ordering comparison initiation, after a prescribed delay time has passed since the comparison data was supplied to the DA converting section, wherein

the comparing section begins comparing the input signal to the comparison signal at the comparison initiation timing indicated by the comparison control signal.

4. The AD conversion apparatus according to claim 3 , wherein

the timing generating section outputs the comparison control signal ordering the reset, after a prescribed delay time has passed since the comparison initiation was ordered,

the comparing section resets the comparison result at the reset timing indicated by the comparison control signal, outputs a positive result signal and a negative result signal representing the comparison result as differential logic values during a comparison period, and outputs a positive result signal and a negative result signal representing logic values fixed at one value during a reset period; and

the completion detecting section outputs the completion signal at a timing when the logic value of the positive result signal is not equal to the logic value of the negative result signal.

5. The AD conversion apparatus according to claim 3 , wherein

the timing generating section outputs the comparison control signal indicating the reset, after a prescribed delay time has passed since the comparison initiation,

the comparing section resets the comparison result at the reset timing indicated by the comparison control signal, outputs a positive result signal and a negative result signal representing the comparison result as differential logic values during a comparison period, and outputs a positive result signal and a negative result signal representing logic values fixed at one value during a reset period; and

the completion detecting section includes:

a differential amplifier that outputs an amplified signal obtained by amplifying a difference between the positive result signal and the negative result signal; and

a comparator that outputs the completion signal at a timing when the absolute value of the amplified signal is greater than a predetermined value.

6. The AD conversion apparatus according to claim 3 , wherein

the timing generating section outputs the comparison control signal indicating the reset, after a prescribed delay time has passed since the comparison initiation, and

the comparing section resets the comparison result at the reset timing indicated by the comparison control signal, the AD conversion apparatus further comprising:

a reset adjusting section that changes the timing of the reset indicated by the comparison control signal for a next conversion target bit, according to a response time, which is from when the comparing section begins the comparison to when the completion detecting section outputs the completion signal.

7. The AD conversion apparatus according to claim 6 , wherein

the reset adjusting section causes the reset timing indicated by the comparison control signal of the next conversion target bit to be earlier when the response time is longer.

8. The AD conversion apparatus according to claim 7 , wherein

the reset adjusting section causes the reset timing indicated by the comparison control signal of the next conversion target bit to be earlier when the response time is longer, on a condition that the conversion target bit be higher than a predetermined bit position.

9. A successive approximation AD conversion apparatus that outputs digital output data corresponding to an analog input signal, comprising:

a bit selecting section that selects a conversion target bit sequentially from a highest bit of the output data;

a data control section that outputs comparison data determining a value of the conversion target bit, each time a conversion target bit is selected;

a DA converting section that outputs an analog comparison signal corresponding to the comparison data;

a comparing section that outputs a comparison result between the input signal and the comparison signal, upon the output of the comparison signal by the DA converting section, and that is reset after outputting the comparison results;

a completion detecting section that, upon detecting that the comparing section has output the comparison result, outputs a completion signal causing the bit selecting section to select a next conversion target bit, prior to the comparing section being reset; and

an output section that outputs output data in which a value of each bit is based on the comparison result by the comparing section, wherein

the DA converting section is a capacitor array DA converter.