P-channel MOS transistor and semiconductor integrated circuit device
View Patent ↗A p-channel MOS transistor includes a gate electrode formed on a silicon substrate via a gate insulating film, a channel region formed below the gate electrode within the silicon substrate, and a p-type source region and a p-type drain region formed at opposite sides of the channel region within the silicon substrate. In the p-channel MOS transistor, first and second sidewall insulating films are arranged on opposing sidewall faces of the gate electrode. First and second p-type epitaxial regions are respectively formed at outer sides of the first and second sidewall insulating films on the silicon substrate, and the first and second p-type epitaxial regions are arranged to be higher than the gate electrode. A stress film that stores tensile stress and covers the gate electrode via the first and second sidewall insulating films is continuously arranged over the first and second p-type epitaxial regions.
1. A p-channel MOS transistor comprising:
a silicon substrate;
a gate electrode formed on the silicon substrate via a gate insulating film;
a channel region formed below the gate electrode within the silicon substrate;
a p-type source region and a p-type drain region that are formed at opposite sides of the channel region within the silicon substrate;
a first sidewall insulating film and a second sidewall insulating film that are formed on opposing sidewall faces of the gate electrode;
a first p-type epitaxial region and a second p-type epitaxial region that are respectively formed at outer sides of the first sidewall insulating film and the second sidewall insulating film on the silicon substrate the first p-type epitaxial region and the second p-type epitaxial region being arranged to have heights larger than a height of the gate electrode; and
a tensile stress film that stores tensile stress and is arranged to cover the gate electrode via the first sidewall insulating film and the second sidewall insulating film, said tensile stress film being arranged to continuously cover the gate electrode, the first and second sidewall insulating films, the first and second p-type epitaxial regions, and depression regions between the first sidewall insulating film and the first p-type epitaxial region and between the second sidewall insulating film and the second p-type epitaxial region,
wherein a bottom of said tensile stress film on the gate electrode is lower than bottoms of said tensile stress film on the first and the second p-type epitaxial regions.
2. The p-channel MOS transistor as claimed in claim 1 , wherein
the first p-type epitaxial region and the second p-type epitaxial region are made of silicon.
3. The p-channel MOS transistor as claimed in claim 1 , wherein
the first p-type epitaxial region and the second p-type epitaxial region are made of silicon-germanium mixed crystal.
4. The p-channel MOS transistor as claimed in claim 3 , wherein
a first concave portion and a second concave portion are respectively formed at outer sides of the first sidewall insulating film and the second sidewall insulating film within the silicon substrate; and
the first p-type epitaxial region and the second p-type epitaxial region are respectively arranged to grow in a perpendicular direction with respect to the silicon substrate from the first concave portion and the second concave portion.
5. The p-channel MOS transistor as claimed in claim 4 , wherein
the first concave portion and the second concave portion have opposing sidewall faces that are defined by crystal faces; and
the opposing side wall faces of the first concave portion and the second concave portion are inclined with respect to each other such that a distance between the first concave portion and the second concave portion toward a bottom side of the silicon substrate is greater than a distance between the first concave portion and the second concave portion toward an interface of the silicon substrate with the gate insulating film.
6. The p-channel MOS transistor as claimed in claim 1 , wherein
the tensile stress film is a silicon nitride film that stores a tensile stress of 0.4-4.0 GPa.