Method of manufacturing silicon carbide semiconductor device
View Patent ↗Stress is exerted to the SiC crystal in the region, in which the carriers of a SiC semiconductor device flow, to change the crystal lattice intervals of the SiC crystal. Since the degeneration of the conduction bands in the bottoms thereof is dissolved, since the inter-band scattering is prevented from causing, and since the effective electron mass is reduced due to the crystal lattice interval change, the carrier mobility in the SiC crystal is improved, the resistance of the SiC crystal is reduced and, therefore, the on-resistance of the SiC semiconductor device is reduced.
1. A method of manufacturing a SiC semiconductor device, the SiC semiconductor device including a SiC substrate of a first conductivity type; a SiC drift layer of the first conductivity type on the substrate; SiC base regions of a second conductivity type contacting with the drift layer; a SiC source region of the first conductivity type contacting with the base region; a gate electrode covering the portion of the base region that is sandwiched between the drift layer and the source region, with a gate insulator film interposed therebetween; a source electrode contacting commonly with the base region and the source region; and a drain electrode on the back surface of the substrate, the method comprising exerting stress to SiC in the region where carriers flow in order to change the crystal lattice intervals of the SiC, wherein stress is exerted on SiC in the region where carriers flow by implanting Ar ions in the SiC in the region where carriers flow and annealing the implanted Ar atoms, in order to exert stress on the SiC in the region where carriers flow and thereby change the crystal lattice intervals of the SiC layer comprising the region where carriers flow.
2. A method of manufacturing a SiC semiconductor device, the SiC semiconductor device including a SiC substrate of a first conductivity type; a SiC drift layer of the first conductivity type on the substrate; SiC base regions of a second conductivity type contacting with the drift layer; a SiC source region of the first conductivity type contacting with the base region; a gate electrode covering the portion of the base region that is sandwiched between the drift layer and the source region, with a gate insulator film interposed therebetween; a source electrode contacting commonly with the base region and the source region; and a drain electrode on the back surface of the substrate, the method comprising exerting stress to SiC in the region where carriers flow in order to change the crystal lattice intervals of the SiC, by implanting Ar ions in the sandwiched portion of the base region, annealing the implanted Ar atoms, and forming a SiC layer comprising the region where carriers flow in contact with the sandwiched portion of the base region, in order to exert stress on the SiC in the region where carriers flow and thereby change the crystal lattice intervals of the SiC layer comprising the region where carriers flow.
3. The method according to claim 1 , wherein stress is exerted on SiC in the region where carriers flow by implanting impurity ions in the sandwiched portion of the base region, annealing the implanted impurity atoms, and forming a SiC layer comprising the region where carriers flow in contact with the sandwiched portion of the base region, in order to exert stress on the SiC in the region where carriers flow and thereby change the crystal lattice intervals of the SiC.