IP Library Granted Patent US 8,093,670
Granted Patent B2
US 8,093,670 · App. 12/178,781 · Granted Jan 10, 2012

Methods and apparatus for integrated circuit having on chip capacitor with eddy current reductions

Assignee: Allegro Microsystems, Inc.
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Quick Facts
Patent No.
US 8,093,670
App. No.
12/178,781
Granted
Jan 10, 2012
Kind
B2
Abstract

Methods and apparatus for providing an integrated circuit including a substrate having a magnetic field sensor, first and second conductive layers generally parallel to the substrate, and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers.

Claims (38)

1. An integrated circuit, comprising:

a substrate having a magnetic field sensor element;

first and second conductive layers generally parallel to the substrate;

a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor; and

first and second terminals, wherein the first terminal is electrically connected to the first conductive layer and the second terminal is electrically connected to the second conductive layer,

wherein the substrate includes circuitry, and the integrated circuit further includes at least one conductive layer to interconnect the circuitry and an insulator layer to electrically insulate the at least one conductive layer,

wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor element for reducing eddy currents in the first and second conductive layers,

wherein the slot in at least one of the first and second conductive layers overlaps with the magnetic field sensor element and extends to an edge of a first one of the first and second conductive layers.

2. The integrated circuit according to claim 1 , wherein the slot includes a first slot in the first conductive layer and a second slot in the second conductive layer, wherein the first and second slots having different geometries.

3. The integrated circuit according to claim 1 , wherein the slot includes a first slot in the first conductive layer and a second slot in the second conductive layer, wherein the first and second slots have substantially similar geometries.

4. The integrated circuit according to claim 1 , wherein the magnetic field sensor element includes a Hall element.

5. The integrated circuit according to claim 1 , wherein the magnetic field sensor element includes a magnetoresistance element.

6. The integrated circuit according to claim 1 , wherein the capacitor overlaps with at least thirty percent of an area of the substrate.

7. The integrated circuit according to claim 1 , wherein the capacitor provides a capacitance from about 100 pF to about 1,500 pF for a substrate ranging in size from about 1 mm 2 to about 10 mm 2 .

8. The integrated circuit according to claim 1 , wherein the first terminal is adapted for coupling to a voltage supply terminal.

9. The integrated circuit according to claim 8 , wherein the second terminal is adapted for coupling to a ground terminal.

10. The integrated circuit according to claim 1 , further including a second substrate in communication with the first substrate, the second substrate having third and fourth conductive layers and a second dielectric layer forming a second on-chip capacitor on the second substrate proximate a second magnetic field sensor element, wherein the second capacitor includes a second capacitor slot including a slot in the third conductive layer to reduce eddy current flow.

11. The integrated circuit according to 10 , wherein the second capacitor slot further includes a slot in the fourth conductive layer.

12. The integrated circuit according to claim 10 , wherein the first and second substrates are of different materials.

13. A method of providing a magnetic field sensor, comprising:

forming a first conductive layer generally parallel to a substrate containing circuitry;

forming a dielectric layer for the first conductive layer;

forming a second conductive layer over the dielectric layer such that the first conductive layer, the dielectric layer, and the second conductive layer form a first capacitor;

forming a slot in the first conductive layer proximate a magnetic field element in the substrate, wherein the slot in at least one of the first and second conductive layers overlaps with the magnetic field sensor and extends to an edge of a first one of the first and second conductive layers; and

providing first and second terminals, wherein the first terminal is coupled to the first conductive layer and the second terminal is coupled to the second conductive layer.

14. The method according to claim 13 , wherein the capacitor overlaps with at least thirty percent of an area of the substrate.

15. The method according to claim 13 , wherein the magnetic field sensor includes a Hall sensor.

16. The method according to claim 13 , wherein the magnetic field sensor includes a magnetoresistance element.

17. The method according to claim 13 , further including forming a second capacitor on a second substrate in communication with the first substrate, and forming a second slot in the second capacitor to reduce eddy currents associated with a second magnetic field sensor.

18. A vehicle, comprising: An integrated circuit, comprising: a substrate having a magnetic field sensor; first and second conductive layers generally parallel to the substrate; and a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor, wherein a slot is formed in at least one of the first and second conductive layers proximate the magnetic field sensor for reducing eddy currents in the first and second conductive layers, wherein the slot in at least one of the first and second conductive layers overlaps with the magnetic field sensor and extends to an edge of a first one of the first and second conductive layers.

19. The vehicle according to claim 18 , wherein the substrate includes circuitry, and the integrated circuit further includes at least one conductive interconnect layer to interconnect the circuitry and an insulator layer to electrically insulate the at least one conductive layer.

20. The vehicle according to claim 18 , further including first and second terminals, wherein the first terminal is electrically connected to the first conductive layer and the second terminal is electrically connected to the second conductive layer.

21. The vehicle according to claim 18 , wherein the slot includes a first slot in the first conductive layer and a second slot in the second conductive layer, wherein the first and second slots have different geometries.

22. An integrated circuit, comprising:

a substrate having a magnetic field sensor;

first and second conductive layers generally parallel to the substrate;

a dielectric layer disposed between the first and second conductive layers such that the first and second conductive layers and the dielectric layer form a capacitor; and

means for reducing eddy currents, wherein the means for reducing eddy currents includes a slot in at least one of the first and second conductive layers overlapping with the magnetic field sensor.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS AT REEL 053957/FRAME 0874 Recorded Nov 1, 2023
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 065420/0572 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2023
From: ALLEGRO MICROSYSTEMS, LLC
To: MORGAN STANLEY SENIOR FUNDING, INC., AS THE COLLATERAL AGENT
Reel/Frame 064068/0459 →
RELEASE OF SECURITY INTEREST IN PATENTS (R/F 053957/0620) Recorded Jun 22, 2023
From: MIZUHO BANK, LTD., AS COLLATERAL AGENT
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 064068/0360 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: MIZUHO BANK LTD., AS COLLATERAL AGENT
Reel/Frame 053957/0620 →
PATENT SECURITY AGREEMENT Recorded Oct 1, 2020
From: ALLEGRO MICROSYSTEMS, LLC
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 053957/0874 →
CONVERSION AND NAME CHANGE Recorded Apr 10, 2013
From: ALLEGRO MICROSYSTEMS, INC.
To: ALLEGRO MICROSYSTEMS, LLC
Reel/Frame 030426/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2008
From: TAYLOR, WILLIAM P.
To: ALLEGRO MICROSYSTEMS, INC.
Reel/Frame 021289/0618 →
Continuity (1)
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