METHOD FOR IMPROVED PROCESS LATITUDE BY ELONGATED VIA INTEGRATION
Interconnect dual damascene structure are fabricated by depositing on a layer of at least one dielectric, a mask forming layer for providing the via-level mask layer of the dual damascene structures; creating an elongated via pattern in the via-level mask layer; depositing a layer of line-level dielectric and creating a line pattern through the layer of line-level dielectric, and transferring the line pattern through the projected intersection of the elongated via-level pattern and of the line-level pattern thereby generating an aligned dual damascene structure. A conductive liner layer is deposited in the dual damascene structure followed by filling the dual damascene structure with a conductive fill metal to form a set of metal lines. The metal and liner layers are planarized.
1 . A Very-Large Scale Integrated (VLSI) device or Ultra-Large Scale Integrated (ULSI) device that comprises an interconnect structure comprising an aligned dual damascene pattern of a line level pattern and an elongated via-level pattern;
a conductive liner layer and conductive fill metal in the aligned dual damascene pattern forming a set of metal lines;
and wherein the conductive liner layer and metal are coplanar with the top layer of the damascene pattern, and
wherein said elongated
via pattern is elongated in the orthogonal direction to said line level pattern; and
wherein said dual damascene structure is self aligned in said orthogonal direction.
2 . The Very-Large Scale Integrated (VLSI) device or Ultra-Large Scale Integrated (ULSI) device of claim 1 , wherein the interconnect structure further comprises mask-forming layers that are hardmask materials.
3 . The Very-Large Scale Integrated (VLSI) device or Ultra-Large Scale Integrated (ULSI) device of claim 1 , wherein the elongated via pattern is elongated by at least 10% of the line-to-line spacing.
4 . The Very-Large Scale Integrated (VLSI) device or Ultra-Large Scale Integrated (ULSI) device of claim 1 , wherein the elongated via pattern is elongated by less than ½ the line-to-line spacing.
5 . The Very-Large Scale Integrated (VLSI) device or Ultra-Large Scale Integrated (ULSI) device of claim 1 , wherein the elongated via pattern is elongated from about 10% to less than ½ the line-to-line spacing.
6 . The Very-Large Scale Integrated (VLSI) device or Ultra-Large Scale Integrated (ULSI) device of claim 1 , wherein the conductive fill material comprises Cu or Ag alloy.
7 . The Very-Large Scale Integrated (VLSI) device or Ultra-Large Scale Integrated (ULSI) device of claim 1 , wherein the interconnect structure further comprises a capping layer.