Patent Assignment
Reel/Frame 052557/0327
Assignment of Assignor's Interest
Recorded: 2020-05-04
Pages: 13
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2020-03-06
Assignee
ELPIS TECHNOLOGIES INC.
1891 ROBERSTON ROAD, SUITE 100, OTTAWA, K2H 5B7, CANADA
Covered Properties
(165)
Adhesive-Bonded Thermal Interface Structures
Adhesive-Bonded Thermal Interface Structures
Application:
16/405,614 →
Publication:
US 2019/0267254
Structures, Methods and Applications for Electrical Pulse Anneal Processes
Structures, Methods and Applications for Electrical Pulse Anneal Processes
Application:
16/288,920 →
Publication:
US 2019/0198347
Package Assembly for Thin Wafer Shipping and Method of Use
Package Assembly for Thin Wafer Shipping and Method of Use
Semiconductor Structures Having Low Resistance Paths Throughout a Wafer
Application:
16/534,045 →
Publication:
US 2019/0362977
Method of Manufacturing Chip-on-Chip Structure Comprising Sinterted Pillars
Chip-On-Chip Structure and Methods of Manufacture
Application:
16/388,113 →
Publication:
US 2019/0244926
Chip-On-Chip Structure Comprising Sintered Pillars
Application:
15/083,852 →
Publication:
US 2016/0365329
Backside Contact to a Final Substrate
Backside Contact to a Final Substrate
Backside Contact to a Final Substrate
Method of Optimizing Wire Rc for Device Performance and Reliability
Protective Liner Between a Gate Dielectric and a Gate Contact
Application:
16/111,300 →
Publication:
US 2019/0013238
Semiconductor Nanowire Fabrication
Multipart Lid for a Semiconductor Package with Multiple Components
Cmos Structures and Methods Using Self-Aligned Dual Stressed Layers
Application:
12/424,981 →
Publication:
US 2009/0194819
Reduction of Edge Chipping During Wafer Handling
Application:
13/774,045 →
Publication:
US 2013/0160705
Microstructure Modification in Copper Interconnect Structures
Application:
13/849,562 →
Publication:
US 2013/0285245
Semiconductor Structure with Integrated Passive Structures
Semiconductor Structure with Integrated Passive Structures
Application:
16/274,612 →
Publication:
US 2019/0181037
Semiconductor Structure with Integrated Passive Structures
Application:
16/585,314 →
Publication:
US 2020/0027779
Universal Clamping Fixture to Maintain Laminate Flatness During Chip Join
Application:
13/777,229 →
Publication:
US 2014/0239569
Gas-Controlled Bonding Platform for Edge Defect Reduction During Wafer Bonding
Enhancement of Iso-via Reliability
Enhancement of Iso-via Reliability
Application:
14/201,893 →
Publication:
US 2015/0255388
Die Level Chemical Mechanical Polishing
Application:
14/839,358 →
Publication:
US 2015/0371870
Shallow Trench Isolation Regions Made from Crystalline Oxides
Application:
15/288,014 →
Publication:
US 2017/0025305
Gas Cluster Reactor for Anisotropic Film Growth
Application:
14/831,900 →
Publication:
US 2015/0376791
Gas Cluster Reactor for Anisotropic Film Growth
Application:
14/937,968 →
Publication:
US 2016/0071723
Diffusion Barrier Layer Formation
Application:
16/118,883 →
Publication:
US 2018/0374746
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Application:
16/577,443 →
Publication:
US 2020/0020598
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Application:
16/577,571 →
Publication:
US 2020/0013682
Method and Structure for Forming a Dense Array of Single Crystalline Semiconductor Nanocrystals
Preventing Strained Fin Relaxation
Spacer for Trench Epitaxial Structures
Spacer for Trench Epitaxial Structures
Advanced Chip to Wafer Stacking
Application:
15/041,060 →
Simultaneously Fabricating a High Voltage Transistor and a Finfet
Lid Attach Optimization to Limit Electronic Package Warpage
Structure and Method to Suppress Work Function Effect by Patterning Boundary Proximity in Replacement Metal Gate
Application:
16/401,141 →
Publication:
US 2019/0259754
Self-Aligned Low Dielectric Constant Gate Cap and a Method of Forming the Same
SiGe FINS FORMED ON A SUBSTRATE
Application:
16/358,227 →
Publication:
US 2019/0214253
SiGe FINS FORMED ON A SUBSTRATE
Application:
16/358,240 →
Publication:
US 2019/0214254
Field Effect Transistor Gate Stack
Application:
16/026,209 →
Publication:
US 2018/0330996
Finfet with Reduced Parasitic Capacitance
Application:
16/402,264 →
Publication:
US 2019/0259852
Client-Initiated Leader Election in Distributed Client-Server Systems
Application:
16/207,283 →
Publication:
US 2019/0104203
Optical Device with Precoated Underfill
Application:
15/287,582 →
Publication:
US 2017/0146741
Three-Dimensional Monolithic Vertical Field Effect Transistor Logic Gates
Three-Dimensional Stacked Vertical Transport Field Effect Transistor Logic Gate with Buried Power Bus
Application:
16/360,360 →
Publication:
US 2019/0221484
Vertical Transport Fin Field Effect Transistor with Asymmetric Channel Profile
Structure and Method Using Metal Spacer for Insertion of Variable Wide Line Implantation in Sadp/Saqp Integration
Controlling Gate Profile by Inter-Layer Dielectric (Ild) Nanolaminates
Inverse Tone Direct Print Euv Lithography Enabled by Selective Material Deposition
Application:
16/406,359 →
Publication:
US 2019/0355625
Indium Gallium Arsenide Metal Oxide Semiconductor Field Effect Transistor Having a Low Contact Resistance to Metal Electrode
Application:
16/682,537 →
Publication:
US 2020/0083342
Vertical Transport Fets Having a Gradient Threshold Voltage
Vertical Transport Fets Having a Gradient Threshold Voltage
Local Wiring in Between Stacked Devices
Application:
16/667,132 →
Publication:
US 2020/0075429
Dielectric Gap Fill Evaluation for Integrated Circuits
Effective Junction Formation in Vertical Transistor Structures by Engineered Bottom Source/Drain Epitaxy
Effective Junction Formation in Vertical Transistor Structures by Engineered Bottom Source/Drain Epitaxy
Application:
16/369,921 →
Publication:
US 2019/0229204
Vfet Metal Gate Patterning for Vertical Transport Field Effect Transistor
Vertical FET with Sharp Junctions
Application:
16/259,412 →
Publication:
US 2019/0157427
Transistor with Asymmetric Source/Drain Overlap
Application:
16/291,931 →
Publication:
US 2019/0393345
Long Channels for Transistors
Application:
16/391,826 →
Publication:
US 2019/0252520
Long Channels for Transistors
Application:
16/392,018 →
Publication:
US 2019/0252497
Methods and Structures for Forming Uniform Fins When Using Hardmask Patterns
Self-Aligned Vertical Field-Effect Transistor with Epitaxially Grown Bottom and Top Source Drain Regions
Application:
16/284,792 →
Publication:
US 2019/0189522
Monolithic Co-Integration of Mosfet and Jfet for Neuromorphic/Cognitive Circuit Applications
Application:
16/354,885 →
Publication:
US 2019/0214309
Four Terminal Stacked Complementary Junction Field Effect Transistors
Application:
16/242,535 →
Publication:
US 2019/0140109
Vertical Field Effect Transistor (Vfet) Programmable Complementary Metal Oxide Semiconductor Inverter
Application:
16/444,639 →
Publication:
US 2019/0304968
High Speed Ge P-Channel Ge/Side/Si Heterostructure Field Effect Transistor
Application:
60/124,299 →
Dielectric material and process of insulating a semiconductor device using same
Application:
09/893,104 →
Publication:
US 2003/0008129
Method for Improved Process Latitude by Elongated via Integration
Application:
12/180,882 →
Publication:
US 2008/0284031
Techniques for improving bond pad performance
Application:
11/115,936 →
Publication:
US 2006/0244138
Method of Forming Semiconductor Film and Photovoltaic Device Including the Film
Application:
12/606,210 →
Publication:
US 2011/0094557
Lateral Oxidation of Nfet and Pfet High-K Gate Stacks
Application:
16/406,443 →
Publication:
US 2019/0267243
Lateral Oxidation of Nfet High-K Gate Stacks
Application:
61/987,620 →
Photovoltaic Cells with Copper Grid
Application:
13/604,223 →
Publication:
US 2013/0065351
SELF-ALIGNED STRUCTURE FOR BULK FinFET
Application:
14/015,967 →
Publication:
US 2014/0306274
Substrate Holder Assembly for Controlled Layer Transfer
Application:
14/024,685 →
Publication:
US 2014/0312576
SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL
Application:
61/976,012 →
Thin Film Interconnects with Large Grains
P-Fet with Graded Silicon-Germanium Channel
Application:
14/221,339 →
Publication:
US 2015/0270344
P-Fet with Graded Silicon-Germanium Channel
Application:
14/934,191 →
Publication:
US 2016/0064210
Self-Cut Sidewall Image Transfer Process
Techniques for Fabricating Reduced-Line-Edge-Roughness Trenches for Aspect Ratio Trapping
Application:
15/206,643 →
Publication:
US 2016/0322226
Techniques for Creating a Local Interconnect Using a SOI Wafer
Extended Contact Area Using Undercut Silicide Extensions
Application:
16/412,526 →
Publication:
US 2019/0267464
Semiconductor Device Having Self-Aligned Gate Contacts
Application:
61/976,073 →
Low External Resistance Channels in Iii-V Semiconductor Devices
Silicon Germanium-on-Insulator Formation by Thermal Mixing
Application:
16/407,892 →
Publication:
US 2019/0267475
SiGe On Insulator Formation By Thermal Mixing of Silicon and Germanium Layers on GeOI and SOI Substrates
Application:
61/939,262 →
Silicon Germanium-on-Insulator Formation by Thermal Mixing
Application:
15/237,235 →
Publication:
US 2016/0358774
Self-Forming Spacers Using Oxidation
Hetero-Integration of Iii-N Material on Silicon
Application:
16/014,210 →
Publication:
US 2018/0315591
Method of Hetero-integration of Crack-free GaN Materials & Devices on Silicon-on-insulator Substrates
Application:
62/024,503 →
Semiconductor Device with Buried Local Interconnects
Implementing a Hybrid Finfet Device and Nanowire Device Utilizing Selective Sgoi
Application:
16/430,539 →
Publication:
US 2019/0288012
Charge Carrier Transport Facilitated by Strain
Application:
16/543,957 →
Publication:
US 2019/0378929
Reducing Autodoping of III-V Semiconductors By Atomic Layer Epitaxy (ALE)
Application:
16/047,952 →
Publication:
US 2018/0342392
Wafer Stacking for Integrated Circuit Manufacturing
Application:
16/432,377 →
Publication:
US 2019/0326190
Porous Silicon Relaxation Medium for Dislocation Free Cmos Devices
Method and Structure for Forming Finfet Cmos with Dual Doped Sti Regions
Application:
15/357,201 →
Publication:
US 2017/0069541
Gate Planarity for Finfet Using Dummy Polish Stop
Application:
15/639,354 →
Publication:
US 2017/0309729
Self-Aligned Punch Through Stopper Liner for Bulk Finfet
Uniform Height Tall Fins with Varying Silicon Germanium Concentrations
Application:
14/856,930 →
Publication:
US 2017/0084454
Porous Fin as Compliant Medium to Form Dislocation-Free Heteroepitaxial Films
Application:
16/020,090 →
Publication:
US 2018/0308691
Dual Silicide Liner Flow for Enabling Low Contact Resistance
Dual Silicide Liner Flow for Enabling Low Contact Resistance
Application:
15/157,803 →
Publication:
US 2017/0125338
Field Effect Transistor Including Strained Germanium Fins
Application:
15/912,740 →
Publication:
US 2018/0197780
Decoupling Capacitor on Strain Relaxation Buffer Layer
Stoplayer
Application:
16/272,844 →
Publication:
US 2019/0206864
Stop Layer Through Ion Implantation For Etch Stop
Application:
15/417,907 →
Publication:
US 2017/0148790
Reactive Ion Etching Assisted Lift-Off Processes for Fabricating Thick Metallization Patterns with Tight Pitch
Enhanced via Fill Material and Processing for Dual Damascene Integration
Application:
15/863,675 →
Publication:
US 2018/0138084
Bottom Source/Drain Silicidation for Vertical Field-Effect Transistor (Fet)
Application:
15/654,879 →
Publication:
US 2017/0316945
Bottom Source/Drain Silicidation for Vertical Field-Effect Transistor (Fet)
Single Process for Liner and Metal Fill
Patterned Gate Dielectrics for Iii-V-Based Cmos Circuits
Application:
16/671,637 →
Publication:
US 2020/0066724
ROBUST HIGH PERFORMANCE LOW HYDROGEN SILICON CARBON NITRIDE (SiCNH) DIELECTRICS FOR NANO ELECTRONIC DEVICES
Application:
16/250,188 →
Publication:
US 2019/0172704
Lateral Bipolar Junction Transistor with Abrupt Junction and Compound Buried Oxide
Lateral Bipolar Junction Transistor with Abrupt Junction and Compound Buried Oxide
Application:
16/502,271 →
Publication:
US 2019/0326397
Well and Punch Through Stopper Formation Using Conformal Doping
Well and Punch Through Stopper Formation Using Conformal Doping
Well and Punch Through Stopper Formation Using Conformal Doping
Application:
15/332,656 →
Publication:
US 2017/0256543
Fabrication of a Vertical Transistor with Self-Aligned Bottom Source/Drain
Application:
16/682,687 →
Publication:
US 2020/0083106
Method and Structure to Fabricate a Nanoporous Membrane
High Density Programmable E-Fuse Co-Integrated with Vertical Fets
Power Decoupling Attachment
High Aspect Ratio Gates
High Aspect Ratio Gates
Application:
16/058,409 →
Publication:
US 2018/0350605
Wimpy Device by Selective Laser Annealing
Conductive Contacts in Semiconductor on Insulator Substrate
Conductive Contacts in Semiconductor on Insulator Substrate
Barrier Planarization for Interconnect Metallization
Application:
15/463,877 →
Publication:
US 2018/0114718
Barrier Planarization for Interconnect Metallization
Application:
15/822,542 →
Publication:
US 2018/0114719
On-Chip Mim Capacitor
Self-Aligned Spacer for Cut-Last Transistor Fabrication
Application:
16/032,563 →
Publication:
US 2018/0323280
Integrated Gate Driver
Sacrificial Cap for Forming Semiconductor Contact
Heterogeneous Metallization Using Solid Diffusion Removal of Metal Interconnects
Application:
15/434,335 →
Publication:
US 2018/0090372
Finfets with Controllable and Adjustable Channel Doping
Application:
16/256,443 →
Publication:
US 2019/0157267
Finfets with Controllable and Adjustable Channel Doping
Semiconductor Device with Self-Aligned Carbon Nanotube Gate
Gate Height and Spacer Uniformity
Semiconductor Device and Method of Forming the Semiconductor Device
Semiconductor Device and Method of Forming the Semiconductor Device
Image Transfer Using Euv Lithographic Structure and Double Patterning Process
Application:
15/798,659 →
Publication:
US 2018/0204724
Resistor Fins
Forming on-Chip Metal-Insulator-Semiconductor Capacitor
Application:
16/571,690 →
Publication:
US 2020/0013773
FORMATION OF COMMON INTERFACIAL LAYER ON Si/SiGe DUAL CHANNEL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR DEVICE
Removal of Trilayer Resist Without Damage to Underlying Structure
Application:
16/001,248 →
Publication:
US 2018/0286680
Removal of Trilayer Resist Without Damage to Underlying Structure
Formation of Full Metal Gate to Suppress Interficial Layer Growth
Application:
16/293,853 →
Publication:
US 2019/0198500
Wrapped Contacts with Enhanced Area
Gate-Last Semiconductor Fabrication with Negative-Tone Resolution Enhancement
Application:
16/352,348 →
Publication:
US 2019/0214315
Fin-Type Fet with Low Source or Drain Contact Resistance
Fin-Type Fet with Low Source or Drain Contact Resistance
Application:
15/681,476 →
Publication:
US 2019/0058044
Dual Channel Silicon/Silicon Germanium Complementary Metal Oxide Semiconductor Performance with Interface Engineering
Forming a Combination of Long Channel Devices and Vertical Transport Fin Field Effect Transistors on the Same Substrate
Application:
16/507,843 →
Publication:
US 2019/0334033
Forming a Combination of Long Channel Devices and Vertical Transport Fin Field Effect Transistors on the Same Substrate
Application:
16/507,683 →
Publication:
US 2019/0341489
Related Assignments
(19)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Mar 25, 2013
From: CABRAL, CYRIL, JR.; GAMBINO, JEFFREY P.; HUANG, QIANG; NOGAMI, TAKESHI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 030073/0890 →
Assignment of Assignor's Interest
Mar 29, 2016
From: GRAF, RICHARD S.; LEONARD, JAY F.; WEST, DAVID J.; WILSON, CHARLES H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 038127/0383 →
Assignment of Assignor's Interest
Oct 6, 2016
From: CORBIN, DAMYON L.; MUSANTE, CHARLES F.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 039959/0129 →
Assignment of Assignor's Interest
Nov 2, 2017
From: GAMBINO, JEFFREY P.; JAFFE, MARK D.; SHANK, STEVEN M.; STAMPER, ANTHONY K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044023/0694 →
Assignment of Assignor's Interest
Feb 6, 2018
From: CLEVENGER, LAWRENCE A.; LI, BAOZHEN; PETERSON, KIRK D.; SHEETS, JOHN E., II
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 044837/0593 →
Assignment of Assignor's Interest
May 31, 2018
From: GAMBINO, JEFFREY P.; JAFFE, MARK D.; SHANK, STEVEN M.; STAMPER, ANTHONY K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 045957/0379 →
Assignment of Assignor's Interest
Jun 25, 2018
From: ABOU-KHALIL, MICHEL J.; GAUTHIER, ROBERT J., JR.; LEE, TOM C.; LI, JUNJUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 046191/0001 →
Assignment of Assignor's Interest
Aug 24, 2018
From: CLEVENGER, LAWRENCE A.; LI, BAOZHEN; PETERSON, KIRK D.; WANG, JUNLI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 046691/0757 →
Assignment of Assignor's Interest
Dec 6, 2018
From: BORG, MATTIAS BENGT; MOSELUND, KIRSTEN EMILIE; REIL, HEIKE E.; SCHMID, HEINZ
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 047696/0530 →
Assignment of Assignor's Interest
Jan 17, 2019
From: GRAF, RICHARD S.; LEONARD, JAY F.; WEST, DAVID J.; WILSON, CHARLES H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048051/0035 →
Assignment of Assignor's Interest
Feb 28, 2019
From: ABOU-KHALIL, MICHEL J.; GAUTHIER, ROBERT J., JR.; LEE, TOM C.; LI, JUNJUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048469/0887 →
Assignment of Assignor's Interest
Apr 18, 2019
From: GRAF, RICHARD S.; LEONARD, JAY F.; WEST, DAVID J.; WILSON, CHARLES H.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048929/0540 →
Assignment of Assignor's Interest
May 7, 2019
From: STATHAKIS, KARL; MANN, PHILLIP V.; HOFFMEYER, MARK K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049104/0416 →
Assignment of Assignor's Interest
May 7, 2019
From: ARVIN, CHARLES L.; OSTRANDER, STEVEN P.; TUNGA, KRISHNA R.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049098/0829 →
Assignment of Assignor's Interest
May 7, 2019
From: STATHAKIS, KARL; MANN, PHILLIP V.; HOFFMEYER, MARK K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049104/0228 →
Assignment of Assignor's Interest
May 7, 2019
From: GAMBINO, JEFFREY P.; JAFFE, MARK D.; SHANK, STEVEN M.; STAMPER, ANTHONY K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049105/0896 →
Assignment of Assignor's Interest
Aug 7, 2019
From: GAMBINO, JEFFREY P.; HARTSWICK, THOMAS J.; HE, ZHONG-XIANG; STAMPER, ANTHONY K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 049991/0398 →
Assignment of Assignor's Interest
Sep 30, 2019
From: CORBIN, DAMYON L.; MUSANTE, CHARLES F.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 050568/0448 →
Corrective Assignment to Correct the Third Inventor's Name Previously Recorded at Reel: 47696 Frame: 530. Assignor(S) Hereby Confirms the Assignment.
Jan 13, 2020
From: BORG, MATTIAS BENGT; MOSELUND, KIRSTEN EMILIE; RIEL, HEIKE E.; SCHMID, HEINZ
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 051573/0772 →