LOCAL WIRING IN BETWEEN STACKED DEVICES
Semiconductor devices and methods are provided to fabricate field effect transistor (FET) devices having local wiring between the stacked devices. For example, a semiconductor device includes a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer. The semiconductor device further includes a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer, wherein the first and second FET devices are in a stacked configuration. The semiconductor device further includes one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.
1 . A semiconductor device, comprising:
a first field-effect transistor (FET) device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer;
a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration and further wherein the second source/drain layer is disposed on the first source/drain layer; and
one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.
2 . The semiconductor device of claim 1 , wherein the first FET device is a PFET device and the second FET device is a NFET device.
3 . The semiconductor device of claim 1 , wherein the first FET device is a NFET device and the second FET device is a PFET device.
4 . The semiconductor device of claim 1 , wherein the one or more conductive vias contain a conductive material comprising one of cobalt, copper, nickel and tungsten.
5 . The semiconductor device of claim 1 , wherein the one or more conductive vias comprise a first conductive via communicative with the first gate structure of the first FET device.
6 . The semiconductor device of claim 5 , wherein the one or more conductive vias comprise a second conductive via communicative with the second source region of the second FET device.
7 . The semiconductor device of claim 6 , wherein the one or more conductive vias comprise a third conductive via communicative with the second gate structure of the second FET device.
8 . The semiconductor device of claim 1 , wherein the one or more conductive vias comprise:
a first conductive via communicative with the first gate structure of the first FET device;
a second conductive via communicative with the second source region of the second FET device; and
a third conductive via communicative with the second gate structure of the second FET device.
9 . The semiconductor device of claim 1 , wherein the first source/drain layer and the second source/drain layer are disposed in an interconnect metal layer.
10 . The semiconductor device of claim 9 , wherein the interconnect metal layer is disposed on an insulator layer.
11 . A stacked vertical FET comprising:
one or more semiconductor devices, wherein one of the semiconductor devices comprises:
a first FET device on a semiconductor substrate, the FET device comprising a first source/drain layer, and a first gate structure comprising a gate dielectric layer and a metal gate layer;
a second FET device comprising a second source/drain layer, and a second gate structure comprising a gate dielectric layer and a metal gate layer; wherein the first and second FET devices are in a stacked configuration and further wherein the second source/drain layer is disposed on the first source/drain layer; and
one or more conductive vias in communication with either the first gate structure of the first FET device or the second gate structure of the second FET device.
12 . The stacked vertical FET of claim 11 , wherein the first FET device is a PFET device and the second FET device is a NFET device.
13 . The stacked vertical FET of claim 11 , wherein the first FET device is a NFET device and the second FET device is a PFET device.
14 . The stacked vertical FET of claim 11 , wherein the one or more conductive vias contain a conductive material comprising one of cobalt, copper, nickel and tungsten.
15 . The stacked vertical FET of claim 11 , wherein the one or more conductive vias comprise a first conductive via communicative with the first gate structure of the first FET device.
16 . The stacked vertical FET of claim 15 , wherein the one or more conductive vias comprise a second conductive via communicative with the second source region of the second FET device.
17 . The stacked vertical FET of claim 16 , wherein the one or more conductive vias comprise a third conductive via communicative with the second gate structure of the second FET device.
18 . The stacked vertical FET of claim 11 , wherein the one or more conductive vias comprise:
a first conductive via communicative with the first gate structure of the first FET device;
a second conductive via communicative with the second source region of the second FET device; and
a third conductive via communicative with the second gate structure of the second FET device.
19 . The stacked vertical FET of claim 11 , wherein the first source/drain layer and the second source/drain layer are disposed in an interconnect metal layer.
20 . The stacked vertical FET of claim 19 , wherein the interconnect metal layer is disposed on an insulator layer.