SELF-ALIGNED VERTICAL FIELD-EFFECT TRANSISTOR WITH EPITAXIALLY GROWN BOTTOM AND TOP SOURCE DRAIN REGIONS
A vertical FET structure includes a bottom source-drain region disposed on a substrate of the first type; a recessed first heterostructure layer disposed on the bottom source-drain region; a first fin disposed on the bottom source-drain region; a dielectric inner spacer disposed on the recessed first heterostructure; an outer spacer disposed on the inner spacer; a high-k and metal gate layer disposed on the outer spacer, the inner spacer, and the channel layer; an interlayer dielectric oxide disposed between the first fin and the outer spacer; a recessed second heterostructure layer disposed on top of the substrate of the first type and high-k and metal gate layer; a dielectric inner spacer disposed on the recessed second heterostructure layer; and a top source-drain region layer disposed on the dielectric inner spacer and recessed second heterostructure layer resulting in the vertical FET. A method for forming the vertical FET is also provided.
1 . A vertical field-effect transistor (FET) structure comprising:
a bottom source-drain region disposed on a substrate of the first type;
a recessed first heterostructure layer disposed on the bottom source-drain region;
a first fin disposed on the bottom source-drain region;
a first dielectric inner spacer disposed on the recessed first heterostructure layer;
an outer spacer disposed on the dielectric inner spacer;
a high-k and metal gate layer disposed on the outer spacer, the first dielectric inner spacer, and the channel layer;
an interlayer dielectric (ILD) oxide disposed between the first fin and the outer spacer;
a recessed second heterostructure layer disposed on top of the substrate of the first type and high-k and metal gate layer;
a second dielectric inner spacer disposed on the recessed second heterostructure layer; and
a top source-drain region layer disposed on the second dielectric inner spacer and recessed second heterostructure layer resulting in the vertical FET.
2 . The vertical FET of claim 1 , wherein the heterostructure layer is silicon germanium.
3 . The vertical FET of claim 1 , wherein and the channel layer is silicon.
4 . The vertical FET of claim 1 , wherein the first dielectric inner spacer is silicon-boron-carbon-nitride (SiBCN).
5 . The vertical FET of claim 1 , wherein the first dielectric inner spacer is silicon nitride.
6 . The vertical FET of claim 1 , wherein the bottom outer spacer can be thicker than the dielectric inner spacer to reduce capacitance.
7 . The vertical FET of claim 1 , wherein a first contact is disposed on the top source-drain region layer.
8 . The vertical FET of claim 1 , wherein a second contact is disposed on the bottom source-drain region layer complete the final transistor.
9 . The vertical FET of claim 1 , wherein the heterostructure layer has a thickness from about 4 to about 10 nm and ranges there between.
10 . The vertical FET of claim 1 , wherein the channel layer has a thickness from about 10 to about 50 nm and ranges there between.
11 . The vertical FET of claim 1 , wherein a hard mask liner is disposed on the sides of the dielectric inner spacer.
12 . The vertical FET of claim 11 , wherein the hard mask liner is silicon nitride.
13 . The vertical FET of claim 1 , wherein the bottom source-drain region layer is silicon.
14 . The vertical FET of claim 1 , wherein the bottom source-drain region layer is silicon-germanium.
15 . The vertical FET of claim 1 , wherein the first fin is formed by using a reactive ion etching (RIE) process.
16 . The vertical FET of claim 1 , wherein the dielectric inner spacer is formed by conformal deposition and then conformal etch-back.
17 . The vertical FET of claim 1 , further comprising an additional bottom source-drain region layer that is epitaxially grown prior to depositing the outer spacer on top of the bottom source-drain region layer.
18 . The vertical FET of claim 1 , wherein an interface between the dielectric inner spacer and the recessed second heterostructure layer has a convex shape.
19 . The vertical FET of claim 1 , wherein the second dielectric inner spacer is silicon-boron-carbon-nitride (SiBCN).
20 . The vertical FET of claim 1 , wherein the second dielectric inner spacer is silicon nitride.