FORMATION OF FULL METAL GATE TO SUPPRESS INTERFICIAL LAYER GROWTH
A semiconductor device is provided and has an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction. The semiconductor device includes first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively. The semiconductor device can also include an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction. Alternatively, the semiconductor device can include an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.
1 . A semiconductor device having an n-channel field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction, the semiconductor device comprising:
first and second fin formations operably disposed in the nFET and pFET bottom junctions, respectively;
and a layer selected from the group consisting of:
an nFET metal gate layer deposited for oxygen absorption onto a high-k dielectric layer provided about the first fin formation in the nFET bottom junction and onto a pFET metal gate layer provided about the second fin formation in the pFET bottom junction; or
an oxygen scavenging layer deposited onto the pFET metal gate layer about the second fin formation in the pFET bottom junction and, with the pFET metal gate layer deposited onto the nFET metal gate layer about the first fin formation in the nFET bottom junction, onto the pFET metal gate layer in the nFET bottom junction.
2 . The semiconductor device according to claim 1 , wherein the nFET metal gate layer comprises a single layer or multiple layers.
3 . The semiconductor device according to claim 1 , wherein the nFET metal gate layer comprises at least one or more of titanium nitride (TiN), titanium aluminum carbide (TiAlC), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), aluminum (Al), titanium aluminum (TiAl), titanium (Ti), other similar materials or combinations thereof or any materials containing metallic Al or metallic Ti.
4 . The semiconductor device according to claim 1 , wherein the pFET metal gate layer comprises a single layer or multiple layers.
5 . The semiconductor device according to claim 1 , wherein the pFET metal gate layer comprises at least one or more of metal nitride or metal carbide including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium carbide (TiC), tantalum carbide (TaC), or pure pFET work function metals including tungsten (W), Nickle (Ni), Platinum (Pt) or Cobalt or combinations thereof.
6 . The semiconductor device according to claim 1 , wherein the oxygen scavenging layer comprises a single layer of at least one or more of titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), aluminum (Al), titanium aluminum (TiAl), titanium (Ti), other similar materials or combinations thereof or any materials containing metallic Al or metallic Ti.
7 . The semiconductor device according to claim 1 , wherein the oxygen scavenging layer comprises multiple layers of at least one or more of titanium nitride (TiN), titanium aluminum carbide (TiAlC), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), aluminum (Al), titanium aluminum (TiAl), titanium (Ti), other similar materials or combinations thereof or any materials containing metallic Al or metallic Ti and metallic nitrides or metallic carbides.
8 . A method of fabricating a semiconductor device having an n-doped field effect transistor (nFET) bottom junction and a p-channel field effect transistor (pFET) bottom junction, the method comprising:
forming first and second fin formations in the nFET and pFET bottom junctions, respectively;
depositing an oxygen scavenging layer onto a pFET metal gate layer about the second fin formation in the pFET bottom junction;
depositing the pFET metal gate layer onto the nFET metal gate layer about the first fin formation in the nFET bottom junction; and
depositing the oxygen scavenging layer onto the pFET metal gate layer in the nFET bottom junction.
9 . The method according to claim 8 , wherein the nFET metal gate layer comprises a single layer or multiple layers.
10 . The method according to claim 8 , wherein the nFET metal gate layer comprises at least one or more of titanium nitride (TiN), titanium aluminum carbide (TiAlC), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), aluminum (Al), titanium aluminum (TiAl), titanium (Ti), other similar materials or combinations thereof or any materials containing metallic Al or metallic Ti and metallic nitrides or metallic carbides.
11 . The method according to claim 8 , wherein the pFET metal gate layer comprises a single layer or multiple layers.
12 . The method according to claim 8 , wherein the pFET metal gate layer comprises at least one or more of metal nitride or metal carbide including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium carbide (TiC), tantalum carbide (TaC), or pure pFET work function metals including tungsten (W), Nickle (Ni), Platinum (Pt) or Cobalt or combinations thereof.
13 . The method according to claim 8 , wherein the oxygen scavenging layer comprises a single layer or multiple layers.
14 . The method according to claim 13 , wherein the single layer of the oxygen scavenging layer comprises at least one or more of titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), aluminum (Al), titanium aluminum (TiAl), titanium (Ti), other similar materials or combinations thereof or any materials containing metallic Al or metallic Ti.
15 . The method according to claim 13 , wherein the multiple layers of the oxygen scavenging layer comprises multiple layers of at least one or more of titanium nitride (TiN), titanium aluminum carbide (TiAlC), tantalum nitride (TaN), tantalum aluminum carbide (TaAlC), aluminum (Al), titanium aluminum (TiAl), titanium (Ti), other similar materials or combinations thereof or any materials containing metallic Al or metallic Ti and metallic nitrides or metallic carbides, and metallic nitrides or metallic carbides.