Spacer for trench epitaxial structures
The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.
1. A method, comprising:
forming source and drain material confined within an area defined by a single spacer material; and
subsequent to the forming the source and drain material, forming a plurality of first-type gate structures and a plurality of second-type gate structures separated from the plurality of the first-type gate structures by the single spacer material, the single spacer material preventing shorting between adjacent ones of the plurality of first-type gate structures and the plurality of second-type gate structures due to a spacing of fins.
2. The method of claim 1 , further comprising:
forming additional spacer material on sidewalls of the first-type gate structures and the second-type gate structures and over a first capping layer; and
forming the single spacer material on a second capping layer in source and drain regions between the first-type gate structures and the second-type gate structures.
3. The method of claim 2 , wherein the single spacer material is a low-k dielectric material which defines trench structures for the source and drain material for the first-type gate structures and the second-type gate structures.
4. The method of claim 2 , wherein the additional spacer material is nitride or oxide material.
5. The method of claim 2 , wherein the forming the source and drain material is an epitaxial growth process.
6. The method of claim 1 , wherein the first-type gate structures are p-type devices and the second-type gate structures are n-type devices.
7. The method of claim 1 , wherein the first-type gate structures are p-type finFET devices and the second-type gate structures are n-type finFET devices.
8. The method of claim 2 , further comprising:
forming the first capping layer on the plurality of the first-type gate structures and the plurality of the second-type gate structures;
forming a first spacer material on sidewalls of the plurality of the first-type gate structures and the plurality of the second-type gate structures and over the first capping layer;
forming the second capping layer on the first spacer material; and
forming the single spacer material on the second capping layer between the plurality of the first-type gate structures and the plurality of the second-type gate structures.
9. The method of claim 8 , wherein the single spacer material defines trench structures for the source and drain material for the plurality of the first-type gate structures and the plurality of the second-type gate structures.
10. The method of claim 1 , wherein the single spacer material is formed on a single side of two gate structures of the plurality of the first-type gate structures and on a single side of two gate structures of the plurality of the second-type gate structures.
11. The method of claim 10 , wherein the two gate structures of the plurality of the first-type gate structures are adjacent to respective ones of the two gate structures of the plurality of the second-type gate structures.
12. The method of claim 1 , wherein the forming the plurality of the first-type gate structures and the plurality of the second-type gate structures comprises:
forming the fins using a sidewall image transfer technique;
depositing a gate dielectric material comprising an oxide on the fins;
depositing gate material on the gate dielectric material; and
depositing a capping material on the gate material.
13. The method of claim 12 , wherein the gate dielectric material is blanket deposited on the fins to a thickness of 2 nm to 5 nm.
14. The method of claim 13 , wherein a gate pitch is less than 80 nm.
15. The method of claim 1 , wherein the single spacer material prevents epitaxial overgrowth of the source and drain material.
16. The method of claim 1 , wherein the single spacer material is SiN, SiBCN, SiOCN, or carbon containing nitride.
17. The method of claim 16 , further comprising depositing the single spacer material using a chemical vapor deposition process.