Spacer for trench epitaxial structures
The disclosure relates to a structure and methods of forming spacers for trench epitaxial structures. The method includes: forming a spacer material between source and drain regions of respective first-type gate structures and second-type gate structures; growing source and drain material about the first-type gate structures, confined within an area defined by the spacer material; and growing source and drain material about the second-type gate structures, confined within an area defined by the spacer material.
1. A method, comprising:
forming a first capping layer by depositing a first capping material on first-type gate structures and second-type gate structures;
forming a first spacer material on sidewalls of the first-type gate structures and the second-type gate structures and over the first capping layer;
forming a second capping layer by depositing a second capping material on the first spacer material;
forming a second spacer material on the second capping layer in source and drain regions between the first-type gate structures and the second-type gate structures;
growing a source and drain material about the first-type gate structures, confined within an area defined by the second spacer material; and
growing the source and drain material about the second-type gate structures, confined within an area defined by the second spacer material.
2. The method of claim 1 , wherein the second spacer material is a low-k dielectric material which defines trench structures for the source and drain material for the first-type gate structures and the second-type gate structures.
3. The method of claim 2 , wherein the second spacer material is nitride or oxide material.
4. The method of claim 1 , wherein the growing source and drain material about the first-type gate structures and the second-type gate structures is an epitaxial growth process.
5. The method of claim 4 , wherein the growing source and drain material about the first-type gate structures is formed while blocking growth of material about the second-type gate structures.
6. The method of claim 5 , further comprising etching a mask over the first-type gate structures to expose the source and drain regions associated with the first-type gate structures, while protecting the source and drain regions of the second-type gate structures.
7. The method of claim 6 , wherein the first-type gate structures is p-type devices and the second-type gate structures is n-type devices.
8. The method of claim 4 , wherein the growing source and drain material about the second-type gate structures is formed while the mask blocks growth about the first-type gate structures.
9. The method of claim 8 , further comprising etching the mask over the second-type gate structures to expose the source and drain regions associated with the second-type gate structures, which is different than material deposited on the source and drain regions of the first-type gate structures after formation of the source and drain regions for the first-type gate structures.
10. The method of claim 1 , wherein the first-type gate structures is p-type devices and the second-type gate structures is n-type devices.
11. The method of claim 1 , wherein the first-type gate structures is p-type finFET devices and the second-type gate structures is n-type finFET devices.
12. A method, comprising:
forming a first type of gate structures and a second type of gate structures;
forming a first capping layer by depositing a first capping material on the first type of gate structures and the second type of gate structures;
forming a spacer on sidewalls on the first type of gate structures and sidewalls on the second type of gate structures and over the first capping layer;
forming a second capping layer by depositing a second capping material on the spacer; and
forming a low-k dielectric spacer material on the second capping layer around edges of trenches for source and drain regions of the first type of gate structures and the second type of gate structures which confines epitaxial source and drain material from shorting between the adjacent ones of the first type of gate structures and the second type of gate structures.
13. The method of claim 12 , wherein the low-k dielectric spacer material is a nitride or oxide material.
14. The method of claim 12 , wherein the epitaxial source and drain material is formed by growing source and drain material confined within the trenches associated with the first-type of gate structures and the second-type gate structures.
15. The method of claim 14 , wherein the growing of the source and drain material about the first-type gate structures is formed while blocking growth of source and drain material about the second-type gate structures.
16. The method of claim 15 , further comprising etching material over the first-type gate structures to expose the source and drain regions thereof, while protecting the source and drain regions of the second-type gate structures.
17. The method of claim 16 , wherein the first-type gate structures is p-type devices and the second-type gate structures is n-type devices.
18. The method of claim 12 , wherein the first-type gate structures are p-type devices and the second-type gate structures are n-type devices.
19. The method of claim 12 , wherein the first-type gate structures are p-type finFET devices and the second-type gate structures are n-type finFET devices.
20. The method of claim 3 , wherein the second spacer material is formed in a location such that the second spacer material prevents epitaxial overgrowth from wrapping around the first-type gate structures and the second-type gate structures during the growing the source and drain material about the first-type gate structures and the growing the source and drain material about the second-type gate structures.