Patent Assignment
Reel/Frame 052561/0161
Assignment of Assignor's Interest
Recorded: 2020-05-04
Pages: 20
Assignor
INTERNATIONAL BUSINESS MACHINES CORPORATION
Executed: 2020-03-06
Assignee
ELPIS TECHNOLOGIES INC.
1891 ROBERTSON ROAD, SUITE 100, OTTAWA, K2H 5B7, CANADA
Covered Properties
(316)
Encapsulated Metal Structures for Semiconductor Devices and Mim Capacitors Including the Same
Patent:
6,368,953 →
Application:
09/567,466 →
Fully Encapsulated Damascene Gates for Gigabit Drams
Patent:
6,504,210 →
Application:
09/599,484 →
Encapsulated Metal Structures for Semiconductor Devices and Mim Capacitors Including the Same
Encapsulated Metal Structures for Semiconductor Devices and Mim Capacitors Including the Same
Method of Fabricating Mim Capacitor with the Encapsulated Metal Structure Serving as the Lower Plate
Cmos Structures and Methods Using Self-Aligned Dual Stressed Layers
Cmos Structures and Methods for Improving Yield
Method of Patterning Multilayer Metal Gate Structures for Cmos Devices
Semiconductor Fin Based Nonvolatile Memory Device and Method for Fabrication Thereof
Method for Removing Threshold Voltage Adjusting Layer with External Acid Diffusion Process
Inducing Stress in Cmos Device
Structures, Methods and Applications for Electrical Pulse Anneal Processes
Integrated Circuit Device with Series-Connected Field Effect Transistors and Integrated Voltage Equalization and Method of Forming the Device
Method to Improve Wet Etch Budget in Feol Integration
Edge Protection Seal for Bonded Substrates
Three Dimensional Integration and Methods of Through Silicon via Creation
Dimensionally Decoupled Ball Limiting Metalurgy
Reduction of Edge Chipping During Wafer Handling
Two-Step Silicide Formation
Minimizing Leakage Current and Junction Capacitance in Cmos Transistors by Utilizing Dielectric Spacers
Converting Metal Mask to Metal-Oxide Etch Stop Layer and Related Semiconductor Structure
Microstructure Modification in Copper Interconnect Structures
Stress-Induced Cmos Device
Interconnect Structure with an Electromigration and Stress Migration Enhancement Liner
Shallow Trench Isolation Structure Having a Nitride Plug
Robotic Device for Substrate Transfer Applications
Integrated Device with Defined Heat Flow
Multilayer Mim Capacitor
On-Chip Radial Cavity Power Divider/Combiner
Replacement-Gate Finfet Structure and Process
Method to Improve Wet Etch Budget in Feol Integration
Three Dimensional Integration and Methods of Through Silicon via Creation
Three Dimensional Integration and Methods of Through Silicon via Creation
Non-Bridging Contact via Structures in Proximity
Integrated Circuit Device with Series-Connected Field Effect Transistors and Integrated Voltage Equalization and Method of Forming the Device
Sidewalls of Electroplated Copper Interconnects
FinFET with Body Contact
Edge Protection Seal for Bonded Substrates
Non-Lithographic Line Pattern Formation
Non-Lithographic Hole Pattern Formation
Semiconductor Structure with Integrated Passive Structures
Implementing Enhanced Power Supply Distribution and Decoupling Utilizing Tsv Exclusion Zone
Signal Path of a Multiple-Patterned Semiconductor Device
Two-Step Silicide Formation
Reduction of Edge Chipping During Wafer Handling
Edge Protection Seal for Bonded Substrates
Signal Path of a Multiple-Patterned Semiconductor Device
Methods of Reducing Defects in Directed Self-Assembled Structures
Finfet with Reduced Capacitance
Interconnect Level Structures for Confining Stitch-Induced via Structures
Thin Channel Mosfet with Silicide Local Interconnect
Grapho-Epitaxy Dsa Process with Dimension Control of Template Pattern
Three Dimensional Integration and Methods of Through Silicon via Creation
Anticipatory Implant for Tsv
Minimizing Leakage Current and Junction Capacitance in Cmos Transistors by Utilizing Dielectric Spacers
Two-Step Silicide Formation
Semiconductor-On-Insulator (Soi) Structures with Local Heat Dissipater(S) and Methods
Package Assembly for Thin Wafer Shipping and Method of Use
Heat Dissipative Electrical Isolation/Insulation Structure for Semiconductor Devices and Method of Making
Sidewalls of Electroplated Copper Interconnects
Sidewalls of Electroplated Copper Interconnects
Sidewalls of Electroplated Copper Interconnects
Microstructure Modification in Copper Interconnect Structures
Structures, Methods and Applications for Electrical Pulse Anneal Processes
Interconnect Structure with an Electromigration and Stress Migration Enhancement Liner
Apparatus and Method for Centering Substrates on a Chuck
Wiring Structure for Trench Fuse Component with Methods of Fabrication
Deep Well Implant Using Blocking Mask
Composite Dielectric Materials with Improved Mechanical and Electrical Properties
Advanced Ultra Low K Sicoh Dielectrics Prepared by Built-in Engineered Pore Size and Bonding Structured with Cyclic Organosilicon Precursors
Die Level Chemical Mechanical Polishing
Selectively Grown Self-Aligned Fins for Deep Isolation Integration
Directional Chemical Oxide Etch Technique
Gas-Controlled Bonding Platform for Edge Defect Reduction During Wafer Bonding
Rework and Stripping of Complex Patterning Layers Using Chemical Mechanical Polishing
Formation of Metal Resistor and E-Fuse
Gas Cluster Reactor for Anisotropic Film Growth
Semiconductor Structures Having Low Resistance Paths Throughout a Wafer
Patterning Process for Fin Implantation
Vertically Integrated Memory Cell
Mol Resistor with Metal Grid Heat Shield
Shallow Trench Isolation Regions Made from Crystalline Oxides
Protective Trench Layer and Gate Spacer in Finfet Devices
Grapho-Epitaxy Dsa Process with Dimension Control of Template Pattern
Non-Lithographic Line Pattern Formation
Non-Lithographic Hole Pattern Formation
Wafer Backside Particle Mitigation
FINFETs CONTAINING IMPROVED STRAIN BENEFIT AND SELF ALIGNED TRENCH ISOLATION STRUCTURES
Patent:
9,240,447 →
Application:
14/465,365 →
Sacrificial Carrier Dicing of Semiconductor Wafers
Diffusion Barrier Layer Formation
Integrated Device with Defined Heat Flow
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Shallow Trench Isolation Structure Having a Nitride Plug
Multilayer Mim Capacitor
Dual Epitaxy Cmos Processing Using Selective Nitride Formation for Reduced Gate Pitch
Cmos Structures and Methods for Improving Yield
Wet Bottling Process for Small Diameter Deep Trench Capacitors
Structure for Metal Oxide Semiconductor Capacitor
Patent:
9,245,884 →
Application:
14/568,531 →
Fin Replacement in a Field-Effect Transistor
Interposer with Lattice Construction and Embedded Conductive Metal Structures
Design Structure for Metal Oxide Semiconductor Capacitor
Trench Metal-Insulator-Metal Capacitor with Oxygen Gettering Layer
Method of Forming Semiconductor Fins on Soi Substrate
Implementing Integrated Circuit Chip Attach in Three Dimensional Stack Using Vapor Deposited Solder Cu Pillars
Patent:
9,299,686 →
Application:
14/598,352 →
Polygon Die Packaging
On-Chip Semiconductor Device Having Enhanced Variability
Patent:
9,391,030 →
Application:
14/625,943 →
Finfet with Reduced Capacitance
Low-Cost Soi Finfet Technology
DIRECTLY FORMING SiGe FINS ON OXIDE
Patent:
9,431,425 →
Application:
14/674,586 →
Dielectric Filling Materials with Ionic Compounds
Multilayer Dielectric Structures with Graded Composition for Nano-Scale Semiconductor Devices
Patent:
9,431,235 →
Application:
14/695,705 →
Graphene Sacrificial Deposition Layer on Beol Copper Liner-Seed for Mitigating Queue-Time Issues Between Liner and Plating Step
Patent:
9,412,654 →
Application:
14/697,056 →
Implementing Integrated Circuit Chip Attach in Three Dimensional Stack Using Vapor Deposited Solder Cu Pillars
Patent:
9,299,591 →
Application:
14/698,224 →
Unidirectional Spacer in Trench Silicide
Method and Structure for Forming a Dense Array of Single Crystalline Semiconductor Nanocrystals
Method for Fabricating Cmos Finfets with Dual Channel Material
Patent:
9,293,373 →
Application:
14/721,574 →
Preventing Strained Fin Relaxation by Sealing Fin Ends
Limiting Electronic Package Warpage with Semiconductor Chip Lid and Lid-Ring
Chip-On-Chip Structure and Methods of Manufacture
Method of Source/Drain Height Control in Dual Epi Finfet Formation
Method of Forming Source/Drain Contacts in Unmerged Finfets
Patent:
9,379,025 →
Application:
14/744,080 →
Backside Contact to Final Substrate
Stable Contact on One-Sided Gate Tie-Down Structure
Semiconductor Structures Having Low Resistance Paths Throughout a Wafer
Semiconductor Structures Having Low Resistance Paths Throughout a Wafer
Semiconductor Structures Having Low Resistance Paths Throughout a Wafer
Enhancement of Iso-via Reliability
Formation of Metal Resistor and E-Fuse
Rework and Stripping of Complex Patterning Layers Using Chemical Mechanical Polishing
Patterning Process for Fin Implantation
Universal Clamping Fixture to Maintain Laminate Flatness During Chip Join
Universal Clamping Fixture to Maintain Laminate Flatness During Chip Join
Client-Initiated Leader Election in Distributed Client-Server Systems
Advanced Ultra Low K Sicoh Dielectrics Prepared by Built-in Engineered Pore Size and Bonding Structured with Cyclic Organosilicon Precursors
Method of Charge Controlled Patterning During Reactive Ion Etching
Patent:
9,496,148 →
Application:
14/850,491 →
Multilayer Mim Capacitor
Sacrificial Carrier Dicing of Semiconductor Wafers
Semiconductor Structure with Integrated Passive Structures
Semiconductor Structure with Integrated Passive Structures
Method of Optimizing Wire Rc for Device Performance and Reliability
Interconnect Level Structures for Confining Stitch-Induced via Structures
Interposer with Lattice Construction and Embedded Conductive Metal Structures
Wiring Structure for Trench Fuse Component with Methods of Fabrication
Spacer for Trench Epitaxial Structures
Structures, Methods and Applications for Electrical Pulse Anneal Processes
Structures, Methods and Applications for Electrical Pulse Anneal Processes
Dual Epitaxy Cmos Processing Using Selective Nitride Formation for Reduced Gate Pitch
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Non-Bridging Contact via Structures in Proximity
Block Copolymers for Directed Self-Assembly Applications
Structure and Process for W Contacts
Patent:
9,406,617 →
Application:
14/945,754 →
Method and Structure of Die Stacking Using Pre-Applied Underfill
Patent:
9,330,946 →
Application:
14/946,904 →
Optical Device with Precoated Underfill
Stacked Nanowire Semiconductor Device
Patent:
9,559,013 →
Application:
14/948,441 →
Reduced Defect Densities in Graded Buffer Layers by Tensile Strained Interlayers
Patent:
9,466,672 →
Application:
14/951,908 →
Fabrication of Semiconductor Junctions
Patent:
9,620,360 →
Application:
14/953,117 →
SiGe FINS FORMED ON A SUBSTRATE
Co-Integration of Different Fin Pitches for Logic and Analog Devices
Patent:
9,397,006 →
Application:
14/959,407 →
Self Heating Reduction for Analog Radio Frequency (Rf) Device
Patent:
9,520,500 →
Application:
14/961,372 →
Finfet with Reduced Capacitance
Elimination of Defects in Long Aspect Ratio Trapping Trench Structures
Patent:
9,570,297 →
Application:
14/963,283 →
Lid Attach Optimization to Limit Electronic Package Warpage
Simultaneously Fabricating a High Voltage Transistor and a Finfet
Fabrication of Higher-K Dielectrics
Partially Dielectric Isolated Fin-Shaped Field Effect Transistor (Finfet)
Patent:
9,537,011 →
Application:
14/968,816 →
Etch Stop in a Dep-Etch-Dep Process
Novel Channel Silicon Germanium Formation Method
Material Removal Process for Self-Aligned Contacts
Self-Aligned Low Dielectric Constant Gate Cap and a Method of Forming the Same
Advanced Chip to Wafer Stacking
Confined Eptaxial Growth for Continued Pitch Scaling
Patent:
9,472,447 →
Application:
14/972,228 →
Laminate Warpage Control
Patent:
9,640,492 →
Application:
14/973,130 →
Implant After Through-Silicon via (Tsv) Etch to Getter Mobile Ions
Structure and Method to Suppress Work Function Effect by Patterning Boundary Proximity in Replacement Metal Gate
Field Effect Transistor Gate Stack
Fabrication of a Cmos Structure
Patent:
9,673,104 →
Application:
15/040,346 →
Elimination of Defects in Long Aspect Ratio Trapping Trench Structures
Patent:
9,502,245 →
Application:
15/042,211 →
Simultaneously Fabricating a High Voltage Transistor and a Finfet
Patent:
9,607,898 →
Application:
15/044,169 →
Fabrication of Higher-K Dielectrics
Patent:
9,478,425 →
Application:
15/045,474 →
Finfet with Reduced Capacitance
Finfet with Reduced Capacitance
On-Chip Semiconductor Device Having Enhanced Variability
High-Chi Block Copolymers for Interconnect Structures by Directed Self-Assembly
Semiconductor Nanowire Fabrication
Method and Apparatus for Single Chamber Treatment
Patent:
9,536,780 →
Application:
15/130,814 →
Client-Initiated Leader Election in Distributed Client-Server Systems
Patent:
9,525,725 →
Application:
15/132,394 →
Novel Channel Silicon Germanium Formation Method
Structure and Process for W Contacts
Structure and Process for W Contacts
Multilayer Dielectric Structures with Graded Composition for Nano-Scale Semiconductor Devices
Confined Eptaxial Growth for Continued Pitch Scaling
Diffusion Barrier Layer Formation
Diffusion Barrier Layer Formation
Fabrication of Semiconductor Fin Structures
Patent:
9,735,010 →
Application:
15/166,645 →
Fabrication of Compound Semiconductor Structures
Stacked Nanowire Semiconductor Device
Semiconductor Structures Having Low Resistance Paths Throughout a Wafer
Semiconductor Structure with Integrated Passive Structures
Semiconductor Structure with Integrated Passive Structures
Non-Lithographic Line Pattern Formation
DIRECTLY FORMING SiGe FINS ON OXIDE
Gate-Stack Structure with a Diffusion Barrier Material
Vertically Integrated Memory Cell
Interposer with Lattice Construction and Embedded Conductive Metal Structures
Protective Liner Between a Gate Dielectric and a Gate Contact
Method of Charge Controlled Patterning During Reactive Ion Etching
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Backside Contact to a Final Substrate
Backside Contact to a Final Substrate
Wafer Stress Control and Topography Compensation
Package Assembly for Thin Wafer Shipping and Method of Use
Client-Initiated Leader Election in Distributed Client-Server Systems
Client-Initiated Leader Election in Distributed Client-Server Systems
Finfet with Reduced Parasitic Capacitance
Partially Dielectric Isolated Fin-Shaped Field Effect Transistor (Finfet)
Finfet with Reduced Capacitance
Self Heating Reduction for Analog Radio Frequency (Rf) Device
Self Heating Reduction for Analog Radio Frequency (Rf) Device
Method and Apparatus for Single Chamber Treatment
Patent:
9,702,042 →
Application:
15/352,917 →
Preventing Strained Fin Relaxation
Semiconductor Devices with Sidewall Spacers of Equal Thickness
Advanced Metal Insulator Metal Capacitor
Semiconductor Structures Having Low Resistance Paths Throughout a Wafer
Fin Replacement in a Field-Effect Transistor
Microstructure Modulation for Metal Wafer-Wafer Bonding
Fabrication of Semiconductor Junctions
Non-Polar, Iii-Nitride Semiconductor Fin Field-Effect Transistor
Patent:
9,978,872 →
Application:
15/467,843 →
Fabricating Contacts of a Cmos Structure
Patent:
9,997,409 →
Application:
15/481,527 →
Centering Substrates on a Chuck
Method and Apparatus for Single Chamber Treatment
Semiconductor Structure with Integrated Passive Structures
Porous Tin Oxide Films
Patent:
10,020,199 →
Application:
15/595,124 →
Trench Metal Insulator Metal Capacitor with Oxygen Gettering Layer
Four Terminal Stacked Complementary Junction Field Effect Transistors
Adhesive-Bonded Thermal Interface Structures
Fabrication of Semiconductor Fin Structures
Enhancement of Iso-via Reliability
Semiconductor Structure with Integrated Passive Structures
Material Removal Process for Self-Aligned Contacts
Material Removal Process for Self-Aligned Contacts
Simultaneously Fabricating a High Voltage Transistor and a Finfet
Utilizing Multiple Layers to Increase Spatial Frequency
Direct Gate Patterning for Vertical Transport Field Effect Transistor
Patent:
10,176,997 →
Application:
15/700,246 →
Vertical FET with Sharp Junctions
Structure and Method to Suppress Work Function Effect by Patterning Boundary Proximity in Replacement Metal Gate
Self-Aligned Vertical Field-Effect Transistor with Epitaxially Grown Bottom and Top Source Drain Regions
Backside Contact to a Final Substrate
Limiting Electronic Package Warpage
Transistor Having a High Germanium Percentage Fin Channel and a Gradient Source/Drain Junction Doping Profile
Patent:
10,236,346 →
Application:
15/793,195 →
Adhesive-Bonded Thermal Interface Structures for Integrated Circuit Cooling
Multilayer Dielectric Structures with Graded Composition for Nano-Scale Semiconductor Devices
Diffusion Barrier Layer Formation
Backside Contact to a Final Substrate
Fabricating Contacts of a Cmos Structure
Patent:
9,984,929 →
Application:
15/800,243 →
Utilizing Multiple Layers to Increase Spatial Frequency
Tone Inversion Integration for Phase Change Memory
Patent:
10,211,054 →
Application:
15/802,547 →
Transistor with Asymmetric Spacers
Patent:
10,134,859 →
Application:
15/808,869 →
Non-Bridging Contact via Structures in Proximity
Gas-Controlled Bonding Platform for Edge Defect Reduction During Wafer Bonding
Low-Resistivity Metallic Interconnect Structures
Patent:
10,224,242 →
Application:
15/812,033 →
Advanced Chip to Wafer Stacking
Advanced Chip to Wafer Stacking
Monolithic Co-Integration of Mosfet and Jfet for Neuromorphic/Cognitive Circuit Applications
Vfet Metal Gate Patterning for Vertical Transport Field Effect Transistor
Patent:
10,236,219 →
Application:
15/820,603 →
Gas-Controlled Bonding Platform for Edge Defect Reduction During Wafer Bonding
Local Wiring in Between Stacked Devices
Patent:
10,211,109 →
Application:
15/826,076 →
Multipart Lid for a Semiconductor Package with Multiple Components
Source and Drain Formation Using Self-Aligned Processes
Patent:
10,153,159 →
Application:
15/827,108 →
Low-Cost Soi Finfet Technology
Vertical Transport Fets Having a Gradient Threshold Voltage
Patent:
10,170,577 →
Application:
15/830,963 →
Self-Aligned Low Dielectric Constant Gate Cap and a Method of Forming the Same
Controlling Gate Profile by Inter-Layer Dielectric (Ild) Nanolaminates
Patent:
10,249,730 →
Application:
15/838,312 →
Adhesive-Bonded Thermal Interface Structures
Three-Dimensional Stacked Vertical Transport Field Effect Transistor Logic Gate with Buried Power Bus
Three-Dimensional Monolithic Vertical Field Effect Transistor Logic Gates
Patent:
10,217,674 →
Application:
15/840,897 →
Long Channels for Transistors
Long Channels for Transistors
Methods and Structures for Forming a Tight Pitch Structure
Methods and Structures for Forming Uniform Fins When Using Hardmask Patterns
Dielectric Gap Fill Evaluation for Integrated Circuits
Effective Junction Formation in Vertical Transistor Structures by Engineered Bottom Source/Drain Epitaxy
Vertical FETS with Different Gate Lengths and Spacer Thicknesses
Patent:
10,141,448 →
Application:
15/853,822 →
Finfet with Reduced Parasitic Capacitence
Indium Gallium Arsenide Metal Oxide Semiconductor Field Effect Transistor Having a Low Contact Resistance to Metal Electrode
Patent:
10,290,719 →
Application:
15/855,273 →
Vertical Transport Fet with Two or More Gate Lengths
Stacked Vertical Transistor Device for Three-Dimensional Monolithic Integration
Patent:
10,283,411 →
Application:
15/860,031 →
Structure and Method Using Metal Spacer for Insertion of Variable Wide Line Implantation in Sadp/Saqp Integration
Patent:
10,276,434 →
Application:
15/860,166 →
Vertical Transport Fin Field Effect Transistor with Asymmetric Channel Profile
Patent:
10,297,668 →
Application:
15/876,905 →
Finfet with Reduced Parasitic Capacitance
Transistor with Robust Air Spacer
Patent:
10,211,092 →
Application:
15/881,778 →
Fabricating Contacts of a Cmos Structure
Advanced Metal Insulator Metal Capacitor
Vertical Fin Field Effect Transistor with Integral U-Shaped Electrical Gate Connection
Patent:
10,361,200 →
Application:
15/914,375 →
Method and Apparatus of Fabricating Source and Drain Epitaxy for Vertical Field Effect Transistor
Patent:
10,361,315 →
Application:
15/928,325 →
Method and Structure for Forming a Replacement Contact
Patent:
10,249,533 →
Application:
15/951,787 →
Centering Substrates on a Chuck
Enlarged Contact Area Structure Using Noble Metal Cap and Noble Metal Liner
Patent:
10,361,119 →
Application:
15/966,695 →
Forming Spacer for Trench Epitaxial Structures
Spacer for Trench Epitaxial Structures
Inverse Tone Direct Print Euv Lithography Enabled by Selective Material Deposition
Patent:
10,304,744 →
Application:
15/980,427 →
Porous Tin Oxide Films
Transistor with Asymmetric Source/Drain Overlap
Patent:
10,249,755 →
Application:
16/016,454 →
Tunnel Transistor
Patent:
10,236,364 →
Application:
16/016,477 →
Package Assembly for Thin Wafer Shipping and Method of Use
Tone Inversion Integration for Phase Change Memory
Transistor with Asymmetric Spacers
Source and Drain Formation Using Self-Aligned Processes
Client-Initiated Leader Election in Distributed Client-Server Systems
Local Wiring in Between Stacked Devices
Microstructure Modulation for Metal Wafer-Wafer Bonding
Tunnel Transistor
Patent:
10,483,382 →
Application:
16/278,693 →
Transistor with Asymmetric Source/Drain Overlap
Indium Gallium Arsenide Metal Oxide Semiconductor Field Effect Transistor Having a Low Contact Resistance to Metal Electrode
Fabrication of Compound Semiconductor Structures
Methods and Structures for Forming Uniform Fins When Using Hardmask Patterns
Transistor with Asymmetric Spacers
Related Assignments
(14)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 9, 2000
From: PETRARCA, KEVIN S.; CANAPERI, DONALD; KRISHNAN, MAHADEVAIYER; STEIN, KENNETH JAY
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 010803/0398 →
Assignment of Assignor's Interest
Oct 13, 2000
From: DIVAKARUNI, RAMACHANDRA; GAMBINO, JEFFREY PETER; MANDELMAN, JACK A.; SARDESAI, VIRAJ
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 011224/0051 →
Assignment of Assignor's Interest
May 5, 2006
From: ZHU, HUILONG; YANG, DAEWON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 017578/0263 →
Assignment of Assignor's Interest
Aug 1, 2007
From: ZHU, HUILONG; YANG, DAEWON
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019630/0348 →
Assignment of Assignor's Interest
Oct 11, 2007
From: DORIS, BRUCE B; WISE, RICHARD S; YAN, HONGWEN; ZHANG, YING
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019948/0041 →
Assignment of Assignor's Interest
Oct 26, 2007
From: ZHU, HUILONG; LUO, ZHIJIONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 020021/0866 →
Assignment of Assignor's Interest
Jun 25, 2009
From: CHEN, KUANG-JUNG; LI, WAI-KIN; DONATON, RICARDO A.; HUANG, WU-SONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022873/0159 →
Assignment of Assignor's Interest
Jul 10, 2009
From: LUO, ZHIJIONG; LIANG, QINGQING; YIN, HAIZHOU; ZHU, HUILONG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 022937/0751 →
Assignment of Assignor's Interest
Sep 4, 2009
From: ABOU-KHALIL, MICHEL J.; GAUTHIER, ROBERT J., JR.; LEE, TOM C.; LI, JUNJUN
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023193/0929 →
Assignment of Assignor's Interest
Sep 21, 2009
From: BRYANT, ANDRES; NOWAK, EDWARD J.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023256/0756 →
Assignment of Assignor's Interest
Oct 1, 2009
From: CUMMINGS, JASON E; EDGE, LISA F; HARAN, BALASUBRAMANIAN S; HORAK, DAVID V
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023310/0940 →
Assignment of Assignor's Interest
Nov 17, 2009
From: FAROOQ, MUKTA G.; KINSER, EMILY; WISE, RICHARD S.; AKINMADE-YUSUFF, HAKEEM B.S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023529/0108 →
Assignment of Assignor's Interest
Jan 14, 2010
From: FAROOQ, MUKTA G; KINSER, EMILY R; WISE, RICHARD; YUSUFF, HAKEEM
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 023782/0861 →
Assignment of Assignor's Interest
Sep 14, 2011
From: CABRAL, CYRIL, JR.; NOGAMI, TAKESHI; GAMBINO, JEFFREY P.; HUANG, QIANG
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 026901/0953 →