IP Library Granted Patent US 8,569,154
Granted Patent B2
US 8,569,154 · App. 13/422,415 · Granted Oct 29, 2013

Three dimensional integration and methods of through silicon via creation

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Quick Facts
Patent No.
US 8,569,154
App. No.
13/422,415
Granted
Oct 29, 2013
Kind
B2
Abstract

A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.

Claims (19)

1. A method comprising:

patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, the exposed first planar area aligned vertically with a first conductor embedded in the structure;

etching to the exposed first planar area to form a cavity having a first depth in the structure;

removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer;

forming a doped portion in the sacrificial substrate layer, the doped portion aligned vertically with a second conductor embedded in the structure different from the first conductor;

etching the cavity to increase the depth of the cavity, the first conductor being exposed in response to the etching of the cavity; and

etching the doped portion to expose an underlying planar area, and etching the underlying planar area to increase the planar area and depth of a portion of the cavity, the second conductor being exposed in response to increasing the planar area and depth.

2. The method of claim 1 , wherein the structure includes a first wafer and a second wafer.

3. The method of claim 1 , wherein the structure includes a first chip and a second chip.

4. The method of claim 1 , wherein the portion of exposed sacrificial substrate layer in the structure is doped with ions deposited at an oblique angle.

5. The method of claim 4 , wherein the oblique angle is between 95 degrees and 175 degrees.

6. The method of claim 1 , wherein the method

further comprises: removing the photoresist layer, the sacrificial substrate layer, and an optical planarization layer;

forming a dielectric portion in the cavity;

removing a portion of the dielectric layer;

depositing a barrier layer on the dielectric layer;

filling the cavity with a conductive material; and

removing the excess conductive material by planarization.

7. The method of claim 6 , wherein the conductive material is operative to electrically connect the first conductor to the second conductor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052561/0161 →