Two-step silicide formation
View Patent ↗One embodiment of the present invention comprises a transistor having a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region. A silicide intermix layer is formed over both the source/drain region and a portion of the extension region. A silicide contact is formed through the silicide intermix layer over the source/drain region.
1. A semiconductor device, comprising:
a transistor having a source/drain region within a substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region;
a silicide intermix layer on top of both the source/drain region and at least a portion of the extension region; and
a silicide contact formed through the silicide intermix layer over the source/drain region.
2. The semiconductor device of claim 1 , wherein the source/drain region comprises a portion of the source/drain region raised over the substrate, and wherein the silicide intermix layer is formed vertically along a side of the raised portion of the source/drain region.
3. The semiconductor device of claim 1 , wherein the silicide contact formed through the silicide intermix layer over the source/drain region consumes less than a length of the source/drain region.
4. The semiconductor device of claim 1 , wherein the silicide contact extends past the silicide intermix layer into the source/drain region.
5. A semiconductor device, comprising:
a transistor having a source/drain region, the source/drain region having a portion within a substrate and a portion raised above the substrate, an extension region within the substrate adjoining the source/drain region and extending toward a gate on the substrate, and a dielectric spacer against the gate wherein the dielectric spacer covers at least part of the extension region;
a silicide contact recessed into the raised portion of the source/drain region; and
a silicide intermix layer extending from a side of the silicide contact, down over a vertical side of the raised portion of the source/drain region, and over a portion of the extension region.
6. The semiconductor device of claim 5 , wherein the silicide contact is a second silicide intermix layer.