Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor

1. A method for fabricating a semiconductor device comprising:

receiving a semiconductor structure including a substrate, the substrate structure further including a fin formed on a portion of the substrate, and a first hard mask disposed on a top surface of the fin;

forming a bottom spacer on the substrate, the bottom spacer being in contact with a bottom portion of the fin;

forming a top spacer in contact with a top portion of the fin;

forming a lateral recess in the substrate under the bottom spacer; and

simultaneously growing a first epitaxy upon the bottom spacer within the lateral recess and a second epitaxy upon the top spacer, the first epitaxy forming a bottom source and drain and the second epitaxy forming a top source and drain.

2. The method of claim 1 , further comprising:

forming a dummy gate upon the bottom spacer, the dummy gate disposed between the bottom spacer and the top spacer.

3. The method of claim 2 , further comprising:

forming a sacrificial spacer upon the top spacer and around a portion of the fin; and

etching portions of the top spacer, the dummy gate, the bottom spacer, and the substrate to form a trench adjacent to the fin.

4. The method of claim 3 , wherein forming the lateral recess includes removing portions of the substrate within the trench under the bottom spacer.

5. The method of claim 4 , further comprising removing the sacrificial spacer.

6. The method of claim 3 , wherein the lateral recess is formed by a lateral etching process.

7. The method of claim 2 , further comprising:

removing the dummy gate; and

forming a metal gate between the bottom spacer and the top spacer.

8. The method of claim 7 , wherein forming the metal gate further includes:

depositing a metal gate material; and

etching the metal gate material such that the metal gate material remains between the bottom spacer and the top spacer.

9. The method of claim 8 , wherein the metal gate material includes a high dielectric constant (high-K) metal gate material.

10. The method of claim 1 , further comprising:

depositing an interlayer dielectric material upon the semiconductor structure; and

forming a contact within the interlayer dielectric material in contact with the top source and drain.

11. The method of claim 1 , further comprising:

depositing an oxide fill upon the bottom spacer, the oxide fill disposed between the bottom spacer and the top spacer.

12. The method of claim 11 , further comprising:

depositing a liner upon the top spacer around the top portion of the fin; and

forming a top recess within the liner around the top portion of the fin, the second epitaxy growing within the top recess.

13. The method of claim 11 , further comprising:

removing the oxide fill; and

forming a forming a metal gate between the bottom spacer and the top spacer.

14. An apparatus comprising:

a semiconductor structure including a substrate, the substrate structure further including a fin formed on a portion of the substrate, and a first hard mask disposed on a top surface of the fin;

a bottom spacer formed on the substrate, the bottom spacer being in contact with a bottom portion of the fin;

a top spacer formed in contact with a top portion of the fin;

a lateral recess formed in the substrate under the bottom spacer; and

a first epitaxy upon the bottom spacer within the lateral recess and a second epitaxy upon the top spacer, the first epitaxy forming a bottom source and drain and the second epitaxy forming a top source and drain, wherein the first epitaxy and the second epitaxy are grown simultaneously.

15. The apparatus of claim 14 , further comprising:

a trench formed adjacent to the fin through portions of the top spacer, the bottom spacer, and the substrate.

16. The apparatus of claim 14 , further comprising:

a metal gate between the bottom spacer and the top spacer.

17. The apparatus of claim 14 , further comprising:

an interlayer dielectric material deposited upon the semiconductor structure; and

a contact formed within the interlayer dielectric material in contact with the top source and drain.

18. A computer usable program product comprising one or more computer-readable storage devices, and program instructions stored on at least one of the one or more storage devices, the stored program instructions comprising:

program instructions to receive a semiconductor structure including a substrate, the substrate structure further including a fin formed on a portion of the substrate, and a first hard mask disposed on a top surface of the fin;

program instructions to form a bottom spacer on the substrate, the bottom spacer being in contact with a bottom portion of the fin;

program instructions to form a top spacer in contact with a top portion of the fin;

program instructions to form a lateral recess in the substrate under the bottom spacer; and

program instructions to simultaneously grow a first epitaxy upon the bottom spacer within the lateral recess and a second epitaxy upon the top spacer, the first epitaxy forming a bottom source and drain and the second epitaxy forming a top source and drain.

19. The computer usable program product of claim 18 , wherein the computer usable code is stored in a computer readable storage device in a data processing system, and wherein the computer usable code is transferred over a network from a remote data processing system.

20. The computer usable program product of claim 18 , wherein the computer usable code is stored in a computer readable storage device in a server data processing system, and wherein the computer usable code is downloaded over a network to a remote data processing system for use in a computer readable storage device associated with the remote data processing system.