Method for fabricating CMOS finFETs with dual channel material
A method of forming dual channel FinFETs is provided. Spaced apart first semiconductor material fins are provided in first and second device regions. A second semiconductor material fin having a lattice constant that differs from the first semiconductor material is formed in a gap located between each first semiconductor material fin and in the first and second device regions. A sacrificial structure is formed on each of the semiconductor material fins and in the first and second device regions. The sacrificial structure and each second semiconductor material fin are selectively removed from the first device region to provide a first gate cavity. A first gate structure is formed in the first gate cavity. The sacrificial structure and each first semiconductor material fin are selectively removed from the second device region to provide a second gate cavity. A second gate structure is formed in the second gate cavity.
1. A method of forming a semiconductor structure, said method comprising:
providing a plurality of spaced apart first semiconductor material fins in a first device region and a second device, wherein each first semiconductor material fin comprises a first semiconductor material and extends upward from a substrate;
forming a second semiconductor material fin in a gap located between each first semiconductor material fin within said first device region and within said second device region, wherein each second semiconductor material fin comprises a second semiconductor material having a lattice constant that differs from the first semiconductor material;
forming a first sacrificial structure over said first device region and a second sacrificial structure over said second device region;
selectively removing said first sacrificial structure and each second semiconductor material fin from said first device region to provide a first gate cavity;
forming a first functional gate structure in said first gate cavity and straddling each first semiconductor material fin;
selectively removing said second sacrificial structure and each first semiconductor material fin from said second device region to provide a second gate cavity; and
forming a second functional gate structure in said second gate cavity and straddling each second semiconductor material fin.
2. The method of claim 1 , wherein said providing said plurality of spaced apart first semiconductor fins comprises:
providing a semiconductor substrate comprising at least said first semiconductor material;
forming a hard mask layer on a surface of said first semiconductor material; and
patterning said hard mask layer and at least an uppermost portion of said first semiconductor material.
3. The method of claim 2 , wherein a portion of said hard mask layer remains on a topmost surface of each first semiconductor material fin, and each remaining portion of said hard mask layer is removed prior to forming said first and second sacrificial structures.
4. The method of claim 1 , wherein a width of each first semiconductor material fin is equal to half a desired fin pitch.
5. The method of claim 1 , wherein said forming said second semiconductor material fin comprises an epitaxial growth process.
6. The method of claim 1 , wherein said lattice constant of said second semiconductor material is within 1 percent of said lattice constant of said first semiconductor material.
7. The method of claim 6 , wherein said first semiconductor material is silicon, and said second semiconductor material is a silicon germanium alloy.
8. The method of claim 1 , further comprising forming an interlevel dielectric material on exposed surfaces of said substrate and surrounding said first device region and said second device region, wherein said forming said interlevel dielectric material is performed after said forming said first and second sacrificial structures, and prior to said selectively removing said first sacrificial structure.
9. The method of claim 1 , wherein a height of each first semiconductor material fin is equal to a height of each second semiconductor material fin and wherein a width of each second semiconductor material fin is substantially equal to a width of each first semiconductor material fin.
10. The method of claim 1 , further comprising thinning each first semiconductor material fin within the first device region after said removing said first sacrificial structure and each second semiconductor material fin from said first device region and prior to said forming said first functional gate structure.
11. The method of claim 10 , wherein said thinning comprises oxidation and etching.
12. The method of claim 1 , further comprising thinning each second semiconductor material fin within the second device region after said removing said second sacrificial structure and each first semiconductor material fin from said second device region and prior to said forming said second functional gate structure.
13. The method of claim 12 , wherein said thinning comprises oxidation and etching.
14. A method of forming a semiconductor structure, said method comprising:
providing a plurality of spaced apart first semiconductor material fins in a first device region and a second device, wherein each first semiconductor material fin comprises a first semiconductor material and extends upward from a substrate;
forming a second semiconductor material fin in a gap located between each first semiconductor material fin within said first device region and within said second device region, wherein each second semiconductor material fin comprises a second semiconductor material having a lattice constant that differs from the first semiconductor material;
forming a first sacrificial structure over said first device region and a second sacrificial structure over said second device region;
selectively removing said second sacrificial structure and each first semiconductor material fin from said second device region to provide a second gate cavity;
forming a second functional gate structure in said second gate cavity and straddling each second semiconductor material fin;
selectively removing said first sacrificial structure and each second semiconductor material fin from said first device region to provide a first gate cavity; and
forming a first functional gate structure in said first gate cavity and straddling each first semiconductor material fin.
15. The method of claim 14 , wherein a width of each first semiconductor material fin is equal to half a desired fin pitch.
16. The method of claim 14 , wherein said lattice constant of said second semiconductor material is within 1 percent of said lattice constant of said first semiconductor material.
17. The method of claim 14 , wherein a height of each first semiconductor material fin is equal to a height of each second semiconductor material fin and wherein a width of each second semiconductor material fin is substantially equal to a width of each first semiconductor material fin.
18. The method of claim 14 , further comprising forming an interlevel dielectric material on exposed surfaces of said substrate and surrounding said first device region and said second device region, wherein said forming said interlevel dielectric material is performed after said forming said first and second sacrificial structures, and prior to said selectively removing said second sacrificial structure.
19. The method of claim 14 , further comprising thinning each second semiconductor material fin within the second device region after said removing said second sacrificial structure and each first semiconductor material fin from said second device region and prior to said forming said second functional gate structure.
20. The method of claim 14 , further comprising thinning each first semiconductor material fin within the first device region after said removing said first sacrificial structure and each second semiconductor material fin from said first device region and prior to said forming said first functional gate structure.