Multilayer dielectric structures with graded composition for nano-scale semiconductor devices
Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.
1. A semiconductor structure, comprising:
a multilayer dielectric structure comprising a stack of dielectric films, wherein the dielectric films comprise at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film;
wherein the first SiCNO film comprises a first composition profile of C, N and O atoms;
wherein the second SiCNO film comprises a second composition profile of C, N and O atoms;
wherein the first and second composition profiles are different; and
wherein a total thickness of the multilayer dielectric structure is about 10 nanometers or less.
2. The semiconductor structure of claim 1 , wherein an atomic percentage of 0 atoms in the first SiCNO film is in a range of about 0% to about 25%, and wherein an atomic percentage of O atoms in the second SiCNO film is in a range of about 5% to about 35%.
3. The semiconductor structure of claim 1 , wherein an atomic percentage of C atoms in the first SiCNO film is in a range of about 10% to about 40%, and wherein an atomic percentage of C atoms in the second SiCNO film is in a range of about 0% to about 30%.
4. The semiconductor structure of claim 1 , wherein an atomic percentage of N atoms in the first and second SiCNO films differs in a range of about 2% to about 20%.
5. The semiconductor structure of claim 1 , wherein multilayer dielectric structure consists only of SiCNO films.
6. The semiconductor structure of claim 1 , wherein the dielectric films comprise at least one or more of a SiN film, a SiNO film, a SiCO, a SiCN film, or a combination thereof.
7. The semiconductor structure of claim 1 , wherein each dielectric film has a thickness in a range of about 1.0 nanometer to about 5 nanometers.
8. The semiconductor structure of claim 1 , wherein the multilayer dielectric structure provides step coverage with a conformality of about 70 percent or greater.
9. The semiconductor structure of claim 1 , wherein the multilayer dielectric structure has an effective dielectric constant of about 5.5 or less.
10. A semiconductor structure, comprising:
a multilayer dielectric structure comprising a stack of dielectric films, wherein the dielectric films comprise at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film;
wherein the first SiCNO film comprises a first composition profile of C, N and O atoms;
wherein the second SiCNO film comprises a second composition profile of C, N and O atoms;
wherein the first and second composition profiles are different; and
wherein the semiconductor structure comprises a BEOL (back-end-of line) structure comprising a copper damascene wire and an ILD (inter-level dielectric) layer, and wherein the multilayer dielectric structure comprises a capping layer that is disposed between the ILD layer and the copper damascene wire.
11. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor device, and wherein the multilayer dielectric structure comprises a stress liner layer that is conformally formed over the transistor device to impart a tensile or compressive stress.
12. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a trench isolation structure formed in a semiconductor substrate, and wherein the multilayer dielectric structure comprises a liner or barrier layer conformally formed on a sidewall and bottom surface of an etched trench of the trench isolation structure.
13. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a through-silicon via (TSV) structure formed in a semiconductor substrate, and wherein the multilayer dielectric structure comprises a liner or barrier layer of the TSV structure.
14. An integrated circuit device comprising the semiconductor structure as recited in claim 1 .
15. The semiconductor structure of claim 1 , wherein the semiconductor structure comprises a transistor device, and wherein the multilayer dielectric structure comprises a spacer formed on a sidewall of a gate structure of the transistor device.