IP Library Granted Patent US 10,529,562
Granted Patent B2
US 10,529,562 · App. 16/371,030 · Granted Jan 7, 2020

Fabrication of compound semiconductor structures

Inventors: Daniele Caimi (Besenbueren, CH); Lukas Czornomaz (Zurich, CH); Jean Fompeyrine (Waedenswil, CH); Emanuele Uccelli (Rueschlikon, CH)
Assignee: International Business Machines Corporation
H01L21/02546H01L21/02381H01L21/02455H01L21/02502H01L21/02639H01L21/02645
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Quick Facts
Patent No.
US 10,529,562
App. No.
16/371,030
Granted
Jan 7, 2020
Kind
B2
Abstract

A semiconductor substrate, comprising a first semiconductor material, is provided and an insulating layer is formed thereon; an opening is formed in the insulating layer. Thereby, a seed surface of the substrate is exposed. The opening has sidewalls and a bottom and the bottom corresponds to the seed surface of the substrate. A cavity structure is formed above the insulating layer, including the opening and a lateral growth channel extending laterally over the substrate. A matching array is grown on the seed surface of the substrate, including at least a first semiconductor matching structure comprising a second semiconductor material and a second semiconductor matching structure comprising a third semiconductor material. The compound semiconductor structure comprising a fourth semiconductor material is grown on a seed surface of the second matching structure. The first through fourth semiconductor materials are different from each other. Corresponding semiconductor structures are also included.

Claims (18)

1. A method for fabricating a compound semiconductor structure, the method comprising:

providing a semiconductor substrate comprising a first semiconductor material;

forming an insulating layer on the semiconductor substrate;

forming an opening in the insulating layer, thereby exposing a seed surface of the substrate, the opening having sidewalls and a bottom, wherein the bottom corresponds to the seed surface of the substrate;

forming a cavity structure above the insulating layer, the cavity structure comprising the opening and a lateral growth channel extending laterally over the substrate;

growing a matching array on the seed surface of the substrate, the matching array comprising at least a first matching structure comprising a second semiconductor material and a second matching structure comprising a third semiconductor material;

growing the compound semiconductor structure comprising a fourth semiconductor material on a seed surface of the matching array;

wherein the first, the second, the third and the fourth semiconductor material are different from each other;

further comprising providing a geometrical constraint in the growth channel to reduce in plane crystalline defects, wherein the geometrical constraint is an in-plane necking of the growth channel in a plane of a top view of the semiconductor structure.

2. A method for fabricating a compound semiconductor structure, the method comprising:

providing a semiconductor substrate comprising a first semiconductor material;

forming an insulating layer on the semiconductor substrate;

forming an opening in the insulating layer, thereby exposing a seed surface of the substrate, the opening having sidewalls and a bottom, wherein the bottom corresponds to the seed surface of the substrate;

forming a cavity structure above the insulating layer, the cavity structure comprising the opening and a lateral growth channel extending laterally over the substrate;

growing a matching array on the seed surface of the substrate, the matching array comprising at least a first matching structure comprising a second semiconductor material and a second matching structure comprising a third semiconductor material;

growing the compound semiconductor structure comprising a fourth semiconductor material on a seed surface of the matching array;

wherein the first, the second, the third and the fourth semiconductor material are different from each other;

further comprising providing a geometrical constraint in the growth channel to reduce in plane crystalline defects, wherein the geometrical constraint is a change of the in-plane direction of the growth channel in a plane of a top view of the semiconductor structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052561/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 31, 2019
From: CAIMI, DANIELE; CZORNOMAZ, LUKAS; FOMPEYRINE, JEAN; UCCELLI, EMANUELE
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 048748/0566 →
Continuity (2)
Continuation 15166825 · May 27, 2016
Related Publication 20190228965A1 · Jul 25, 2019