Interposer with lattice construction and embedded conductive metal structures
A lattice structure is formed in a non-silicon interposer substrate to create large cells that are multiples of through hole pitches to act as islands for dielectric fields. Each unit cell is then filled with a dielectric material. Thereafter, holes (i.e., through holes or blind holes) are created within the dielectric material in the cells. After hole formation, a conductive metal is formed into each of the holes providing an interposer. This method can enable fine pitch processing in organic-based materials, isolates the thermal coefficient of expansion (TCE) stress from metal vias to low TCE carriers and creates a path to high volume, low costs components in panel form.
1. A method of forming an interposer, said method comprising:
creating a lattice structure having a plurality of unit cells in a non-silicon interposer substrate;
filling each unit cell of said plurality of unit cells with a dielectric material;
forming a plurality of holes into said dielectric material of each unit cell;
forming a conductive structure in each hole of said plurality of holes;
forming a hole into each conductive structure;
filling said hole with another dielectric material;
forming a hole in said another dielectric material; and
forming another conductive structure in said hole.
2. The method of claim 1 , wherein said non-silicon interposer substrate comprises a material having a thermal coefficient of expansion of from 0 ppm/° C. to 15 ppm/° C.
3. The method of claim 2 , wherein said material is glass.
4. The method claim 1 , wherein each unit cell of said plurality of unit cells is square, a rectangle, or a triangle.
5. The method of claim 1 , wherein said creating said lattice structure having said plurality of unit cells comprises machining, etching, drilling, or blasting.
6. The method of claim 1 , wherein said forming said plurality of holes into said dielectric material of each unit cell comprises drilling, wet etching, dry etching, electric discharge machining, lithography or any combination thereof.
7. The method of claim 1 , wherein at least a set of said plurality of unit cells extends only partially through said non-silicon interpose substrate, and wherein a step of removing portions of said non-silicon interposer substrate is performed after said forming said conductive structure to reveal a bottommost surface of said conductive structure.
8. The method of claim 1 , further comprising:
forming a hole into said another conductive structure;
filling said hole with a further dielectric material;
forming a hole into said further dielectric material;
forming a further conductive structure in said hole.