Self-aligned vertical field-effect transistor with epitaxially grown bottom and top source drain regions
A vertical FET structure includes a bottom source-drain region disposed on a substrate of the first type; a recessed first heterostructure layer disposed on the bottom source-drain region; a first fin disposed on the bottom source-drain region; a dielectric inner spacer disposed on the recessed first heterostructure; an outer spacer disposed on the inner spacer; a high-k and metal gate layer disposed on the outer spacer, the inner spacer, and the channel layer; an interlayer dielectric oxide disposed between the first fin and the outer spacer; a recessed second heterostructure layer disposed on top of the substrate of the first type and high-k and metal gate layer; a dielectric inner spacer disposed on the recessed second heterostructure layer; and a top source-drain region layer disposed on the dielectric inner spacer and recessed second heterostructure layer resulting in the vertical FET. A method for forming the vertical FET is also provided.
1. A method of forming a vertical field-effect transistor (FET), the method comprising:
depositing a first heterostructure layer over a substrate of a first type;
depositing a channel layer over the first heterostructure layer;
depositing a second heterostructure layer over the channel layer;
forming a first fin having a hard mask thereon, wherein the hard mask is disposed on the second heterostructure layer;
recessing the first and the second heterostructure layers such that they are narrower than the first fin and the hard mask;
filling gaps formed in the recessed first and second heterostructure layers with a dielectric inner spacer;
performing oxidation to form SiO 2 over the substrate of the first type and the channel layer;
depositing a dielectric liner;
directionally etching the dielectric liner over the SiO 2 ;
etching the SiO 2 over the substrate of the first type;
epitaxially growing a bottom source-drain region layer over the substrate of the first type;
conformally etching back a hard mask liner over the bottom source-drain region layer;
depositing an outer spacer on top of the bottom source-drain region layer;
removing the SiO 2 ;
depositing a high-k dielectric layer and metal gate layer on top of the first heterostructure layer;
etching the high-k dielectric layer and metal gate layer to a level below the top hard mask;
filling with interlayer dielectric (ILD) oxide and then performing CMP to the top of hard mask;
etching the hard mask; and
epitaxially growing a top source-drain region layer over the first fin to produce the vertical FET.
2. The method of forming a vertical FET of claim 1 , wherein the first fin is formed by using a reactive ion etching (RIE) process.
3. The method of forming a vertical FET of claim 1 , wherein the dielectric inner spacer is formed by conformal deposition and then conformal etch-back.
4. The method of forming a vertical FET of claim 1 , wherein the channel and bottom oxidation is a low temperature plasma oxidation process.
5. The method of forming a vertical FET of claim 1 , wherein the channel and bottom oxidation uses a regular dry oxidation process.
6. The method of forming a vertical FET of claim 1 , wherein a first contact is deposited on the top source-drain region layer and a second contact is deposited on the bottom source-drain region layer to complete the final transistor.
7. The method of forming a vertical FET of claim 1 , wherein the hard mask is etched selectively using hot phosphoric acid (H3PO4).
8. The method of forming a vertical FET of claim 1 , where an additional bottom source-drain region layer is epitaxially grown prior to depositing an outer spacer on top of the bottom source-drain region layer.
9. The method of forming a vertical FET in claim 1 , wherein a dopant drive-in annealing process is performed after the bottom source-drain region layer grows to form a bottom junction.