Finfet with reduced capacitance

1. A structure comprising:

a gate electrode above and perpendicular to a plurality of semiconductor fins;

a pair of spacers disposed on opposing sides of the gate electrode; and

a gap fill material above a semiconductor substrate, directly below the gate electrode, and between the plurality of fins, wherein the gate electrode separates the gap fill material from each of the plurality of fins.

2. The structure of claim 1 , further comprising:

an epitaxially grown region (“EPI region”) above and between a portion of the plurality of fins not covered by the gate electrode, wherein the pair of spacers isolates the EPI region from the gate electrode.

3. The structure of claim 2 , further comprising:

a dielectric layer above the EPI region.

4. The structure of claim 1 , further comprising:

a dummy gate oxide directly above the semiconductor substrate and directly below the gap fill material, wherein the gate electrode separates the dummy gate oxide from each of the plurality of fins.

5. The structure of claim 4 , wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate, and the dummy gate oxide is directly on top of an insulator layer of the semiconductor-on-insulator substrate.

6. The structure of claim 1 , wherein a top surface of the gap fill material is substantially flush with or below a top surface of the plurality of fins.

7. The structure of claim 1 , wherein the gap fill material comprises a nitride.

8. The structure of claim 1 , wherein the gap fill material is surrounded on two opposite sides by a pair of sidewall spacers.

9. The structure of claim 1 , wherein a lateral thickness of a portion of the gate electrode located between the gap fill material and at least one of the plurality semiconductor fins is approximately equal to a distance between the gap fill material and the at least one of the plurality of semiconductor fins.

10. The structure of claim 1 , wherein the gap fill material is between the pair of spacers.