FinFET with reduced capacitance
An finFET structure including a plurality of fins etched from a semiconductor substrate, a plurality of gates above and perpendicular to the plurality of fins, each comprising a pair of spacers on opposing sides of the gates, and a gap fill material above the semiconductor substrate, below the gate, and between the plurality of fins, wherein the gate separates the gap fill material from each of the plurality of fins.
1. A structure comprising:
a plurality of fins etched from a semiconductor substrate;
a gate electrode above and perpendicular to the plurality of fins, a pair of spacers disposed on opposing sides of the gate electrode; and
a gap fill material above the semiconductor substrate, directly below the gate electrode, and between the plurality of fins, wherein the gate electrode separates the gap fill material from each of the plurality of fins.
2. The structure of claim 1 , further comprising:
an epitaxially grown region (“EPI region”) above and between a portion of the plurality of fins not covered by the gate electrode, wherein the pair of spacers isolates the EPI region from the gate electrode.
3. The structure of claim 2 , further comprising:
a dielectric layer above the EPI region.
4. The structure of claim 1 , wherein a top surface of the gap fill material is substantially flush with or below a top surface of the plurality of fins.
5. The structure of claim 1 , wherein the gap fill material comprises a nitride.
6. The structure of claim 1 , further comprising:
a dummy gate oxide directly above the semiconductor substrate and directly below the gap fill material, wherein the gate electrode separates the dummy gate oxide from each of the plurality of fins.
7. A structure comprising:
a gap fill material disposed between two semiconductor fins and above a semiconductor substrate, the gap fill material is separated from each of the two semiconductor fins by a distance; and
a gate electrode disposed above and perpendicular to the two semiconductor fins, wherein a portion of the gate electrode is located between the gap fill material and each of the two semiconductor fins.
8. The structure of claim 7 , further comprising:
an epitaxially grown region (“EPI region”) above and between a portion of the two semiconductor fins not covered by the gate electrode, wherein a pair of sidewall spacers electrically isolates the EPI region from the gate electrode.
9. The structure of claim 7 , wherein a top surface of the gap fill material is substantially flush with or below a top surface of the two semiconductor fins.
10. The structure of claim 7 , wherein the gap fill material comprises a nitride.
11. The structure of claim 7 , wherein a lateral thickness of the portion of the gate electrode located between the gap fill material and each of the two semiconductor fins is approximately equal to the distance between the gap fill material and each of the two semiconductor fins.
12. The structure of claim 7 , wherein the gap fill material is surrounded on two opposite sides by a pair of sidewall spacers.
13. A structure comprising:
a dummy gate oxide disposed between two semiconductor fins and directly on top of a semiconductor substrate, the dummy gate oxide is separated from each of the two semiconductor fins by a distance;
a gap fill material above and in direct contact with the dummy gate oxide, the gap fill material is separated from each of the two semiconductor fins by the distance; a gate electrode disposed above and perpendicular to the two semiconductor fins,
wherein a portion of the gate electrode is located between the dummy gate oxide and each of the two semiconductor fins, wherein the portion of the gate electrode is located between the gap fill material and each of the two semiconductor fins.
14. The structure of claim 13 , further comprising:
an epitaxially grown region (“EPI region”) above and between a portion of the two semiconductor fins not covered by the gate electrode, wherein a pair of sidewall spacers electrically isolates the EPI region from the gate electrode.
15. The structure of claim 13 , wherein a top surface of the gap fill material is substantially flush with or below a top surface of the two semiconductor fins.
16. The structure of claim 13 , wherein the gap fill material comprises a nitride.
17. The structure of claim 13 , wherein the distance between the dummy gate oxide and each of the two semiconductor fins and the distance between the gap fill material and each of the two semiconductor fins is approximately equal to a height or thickness of the dummy gate oxide.
18. The structure of claim 13 , wherein both the dummy gate oxide and the gap fill material are surrounded on two opposite sides by a pair of sidewall spacers.
19. The structure of claim 13 , wherein the semiconductor substrate comprises a semiconductor-on-insulator substrate, and the dummy gate oxide is directly on top of an insulator layer of the semiconductor-on-insulator.