FinFET with reduced capacitance

1. A structure comprising:

a plurality of fins etched from a semiconductor substrate;

a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode;

a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins; and

an epitaxially grown region (“EPI region”) above a portion of the plurality of fins not covered by the gate electrode, the EPI region separates the gap fill material from each of the plurality of fins.

2. The structure of claim 1 , wherein the pair of sidewall spacers isolate the gate electrode from the EPI region.

3. The structure of claim 1 , further comprising:

a dielectric layer above the EPI region.

4. The structure of claim 1 , wherein a top surface of the gap fill material is substantially flush with or below a top surface of the plurality of fins.

5. The structure of claim 1 , wherein the gap fill material comprises a nitride.

6. The structure of claim 1 , further comprising:

a dummy gate oxide directly above the semiconductor substrate and directly below the gap fill material, wherein the gate electrode separates the dummy gate oxide from each of the plurality of fins, and wherein the EPI region separates the dummy gate oxide from each of the plurality of fins.

7. A structure comprising:

a gap fill material disposed between two semiconductor fins and above a semiconductor substrate, the gap fill material is separated from each of the two semiconductor fins by a distance;

a gate electrode disposed above and perpendicular to the two semiconductor fins, wherein a portion of the gate electrode is located between the gap fill material and each of the two semiconductor fins; and

an epitaxially grown region (“EPI region”) above a portion of the two semiconductor fins not covered by the gate electrode, a portion of the EPI region is located between the gap fill material and each of the two semiconductor fins.

8. The structure of claim 7 , wherein a pair of sidewall spacers are disposed on opposites sides of the gate electrode and electrically isolate the gate electrode from the EPI region.

9. The structure of claim 7 , wherein a top surface of the gap fill material is substantially flush with or below a top surface of the two semiconductor fins.

10. The structure of claim 7 , wherein the gap fill material comprises a nitride.

11. The structure of claim 7 , wherein a lateral thickness of the portion of the gate electrode located between the gap fill material and each of the two semiconductor fins is approximately equal to the distance between the gap fill material and each of the two semiconductor fins.

12. The structure of claim 7 , wherein a lateral thickness of the portion of the EPI region located between the gap fill material and each of the two semiconductor fins is approximately equal to the distance between the gap fill material and each of the two semiconductor fins.

13. The structure of claim 7 , wherein opposite sides of the gap fill material are in direct contact with both the gate electrode and the EPI region.

14. A structure comprising:

a dummy gate oxide disposed between two semiconductor fins and directly on top of a semiconductor substrate, the dummy gate oxide is separated from each of the two semiconductor fins by a distance;

a gap fill material above and in direct contact with the dummy gate oxide, the gap fill material is separated from each of the two semiconductor fins by the distance;

a gate electrode disposed above and perpendicular to the two semiconductor fins, a portion of the gate electrode is located between the dummy gate oxide and each of the two semiconductor fins, the portion of the gate electrode is also located between the gap fill material and each of the two semiconductor fins; and

an epitaxially grown region (“EPI region”) above a portion of the two semiconductor fins not covered by the gate electrode, a portion of the EPI region is located between the dummy gate oxide and each of the two semiconductor fins, and another portion of the EPI region is also located between the gap fill material and each of the two semiconductor fins.

15. The structure of claim 14 , wherein a pair of sidewall spacers are disposed on opposites sides of the gate electrode and electrically isolate the gate electrode from the EPI region.

16. The structure of claim 14 , wherein a top surface of the gap fill material is substantially flush with or below a top surface of the two semiconductor fins.

17. The structure of claim 14 , wherein the gap fill material comprises a nitride.

18. The structure of claim 14 , wherein the distance between the dummy gate oxide and each of the two semiconductor fins and the distance between the gap fill material and each of the two semiconductor fins is approximately equal to a height or thickness of the dummy gate oxide.

19. The structure of claim 14 , wherein a lateral thickness of the portion of the EPI region located between the gap fill material and each of the two semiconductor fins is approximately equal to the distance between the gap fill material and each of the two semiconductor fins.

20. The structure of claim 14 , wherein opposite sides of the gap fill material are in direct contact with both the gate electrode and the EPI region.