Self-aligned low dielectric constant gate cap and a method of forming the same
According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.
1. A method of forming a self-aligned contact, comprising:
forming a gate on a substrate, the gate comprising a lower gate portion formed directly on the substrate, a middle gate layer formed directly on the lower gate portion, and an upper gate portion formed directly on middle gate layer;
wherein the middle gate layer is of a different material than the lower and upper gate portions;
wherein a gate cap is located directly on the substrate and on a top surface of the gate, the gate cap being formed directly on sidewalls of the middle gate layer and directly on sidewalls of the lower gate portion, the gate cap being formed directly on top surfaces of both the upper gate portion and the middle gate layer;
forming a conductive contact on the substrate and adjacent to the gate, the conductive contact comprising a liner layer around a silicide layer, a bottom surface of the liner layer being formed directly on the substrate;
wherein the liner layer is directly on sides of the gate cap, wherein a width of the gate cap is inverse to a width of the liner layer such that the width of the gate cap narrows as the width of the liner layer widens and the width of the gate cap widens as the width of the liner layer narrows;
after forming the conductive contact, removing at least a portion of an interlayer dielectric layer to expose a top surface of the gate cap located on the substrate and on the top surface of the gate;
partially recessing the gate cap to form a recessed area such that the top surface of the gate is not exposed, the recessed gate cap comprising a thickness of 1 to 20 nanometers on the top surface of the gate, the liner layer vertically extending above a top surface of the gate cap after recessing the gate cap;
depositing a low dielectric constant oxide having a dielectric constant of 2.8 to 3.5 on a surface of the partially recessed gate cap in the recessed area; and
polishing a surface of the low dielectric constant oxide to expose a surface of the conductive contact;
wherein removing at least a portion of an interlayer dielectric layer comprises dry etching the interlayer dielectric layer;
wherein the low dielectric constant oxide comprises a porous silicon dioxide or a doped silicon dioxide.