Three dimensional integration and methods of through silicon via creation

1. A method comprising:

patterning a photoresist layer on a structure to define an opening and expose a first planar area on a substrate layer;

forming doped portions on a sacrificial substrate layer of the substrate layer to define an exposed doped portion of the sacrificial substrate layer and an exposed undoped portion of the sacrificial substrate layer;

removing a portion of the photoresist to form a second opening defining a second planar area on the substrate layer; and

etching to form a first cavity having a first depth defined by the first opening to expose a first contact in the structure and to form a second cavity defined by the second opening to expose a second contact in the structure,

wherein the exposed doped portion is more selective to etching than the exposed undoped portion, and

wherein the etching includes etching the doped portion such that the etching of the first cavity and the etching of the doped portion results in openings of different depths.

2. The method of claim 1 , wherein the structure includes a first wafer and a second wafer.

3. The method of claim 1 , wherein the structure includes a first chip and a second chip.

4. The method of claim 1 , wherein the method further comprises:

removing the remaining photoresist layer;

forming a dielectric portion in the cavities;

removing a portion of the dielectric layer;

depositing a barrier layer on the dielectric layer;

filling the cavities with a conductive material; and

removing the excess conductive material by planarization.

5. The method of claim 1 , wherein the conductive material is operative to electrically connect the first conductor to the second conductor.

6. The method of claim 1 , wherein the forming doped portions further includes implanting ions in a planar region of the sacrificial substrate layer to define the exposed doped portion and the exposed undoped portion.