Controlling gate profile by inter-layer dielectric (ILD) nanolaminates
A semiconductor structure includes a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures. A liner of a silicon-containing material is deposited over outer surfaces of the plurality of gate structures; over the liner, an inter-layer dielectric material is deposited. The semiconductor substrate with the deposited liner of silicon-containing material and deposited inter-layer dielectric material is annealed to at least partially consume the liner of silicon-containing material into the inter-layer dielectric material, to control residual stress such that resultant gate structures following the annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.
1. A method comprising:
providing a semiconductor structure including a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures;
depositing over outer surfaces of said plurality of gate structures a liner of a silicon-containing material;
depositing over said liner of silicon-containing material an inter-layer dielectric material; and
annealing said semiconductor substrate with said deposited liner of silicon-containing material and deposited inter-layer dielectric material, to at least partially consume said liner of silicon-containing material into said inter-layer dielectric material, to control residual stress such that resultant gate structures following said annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.
2. The method of claim 1 , wherein said liner of silicon-containing material is completely consumed into said inter-layer dielectric material during said annealing.
3. The method of claim 2 , wherein in said step of depositing said liner of silicon-containing material, said liner has a thickness of from 1-5 nm.
4. The method of claim 3 , wherein in said step of depositing said liner of silicon-containing material, said liner comprises amorphous silicon.
5. The method of claim 4 , wherein in said step of depositing said liner of silicon-containing material, said liner has a thickness of from 2-3 nm.
6. The method of claim 4 , wherein said annealing is carried out at a temperature of from 400-800 C.
7. The method of claim 4 , wherein said annealing is carried out for at least one hour at a temperature of from 500-800 C.
8. The method of claim 6 , wherein, in said providing step, said gate structures comprise dummy gate structures.
9. The method of claim 6 , wherein, in said annealing step, said resultant gate structures following said annealing have sidewalls not varying by more than two degrees from vertical.
10. The method of claim 3 , wherein in said step of depositing said liner of silicon-containing material, said liner comprises SiN.
11. The method of claim 3 , wherein in said step of depositing said liner of silicon-containing material, said liner comprises SiON.
12. The method of claim 3 , wherein in said step of depositing said liner of silicon-containing material, said liner comprises SiC.
13. The method of claim 3 , wherein in said step of depositing said liner of silicon-containing material, said liner comprises SiOC.
14. The method of claim 3 , wherein in said step of depositing said liner of silicon-containing material, said liner comprises SiGe.
15. The method of claim 1 , wherein said resultant gate structures following said annealing step have a depth of at least 100 nm.