Simultaneously fabricating a high voltage transistor and a FinFET
Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top surface of the semiconductor layer in a first region, etching the semiconductor layer and a mask in the first region to expose a top surface of the semiconductor substrate to form a first stack, and etching the semiconductor layer and the mask in the second region to expose a top surface of the fin to form a second stack, epitaxially growing a semiconductor material on a top surface of the fin not covered by the second stack, recessing the first and second stack to expose a top surface of the semiconductor layer, a portion of the mask remains above the semiconductor layer in the first stack, top surfaces of each of the first and second stacks each are substantially flush with one another.
1. A semiconductor structure comprising:
a semiconductor substrate comprising a first region and a second region, wherein
a top surface of a first semiconductor layer above a fin only in the second region is at a greater height than a top surface of the first semiconductor layer in the first region, wherein the height is measured relative to a common surface of the semiconductor substrate;
a first stack in the first region comprising a first dielectric layer, the first semiconductor layer, and a first mask, wherein a bottom surface of the first dielectric layer in the first region is essentially coplanar with a top surface of the semiconductor substrate in the first region, a top surface of the first dielectric layer in the first region is essentially coplanar with a bottom surface of the first semiconductor layer in the first region, and a top surface of the first semiconductor layer in the first region is essentially coplanar with a bottom surface of the first mask in the first region; and
a second stack in the second region comprising the first dielectric layer, the first semiconductor layer, and the first mask, wherein a bottom surface of the first dielectric layer in the second region is essentially coplanar with a top surface of the fin, a top surface of the first dielectric layer in the second region is essentially coplanar with a bottom surface of the first semiconductor layer in the second region, and a top surface of the first semiconductor layer in the second region is essentially coplanar with a bottom surface of the first mask in the second region, wherein
a top surface of the first mask in the first region is essentially coplanar with a top surface of the first mask in the second region.
2. The structure according to claim 1 , wherein the second region comprises an array of fin field effect transistors.
3. The structure according to claim 1 , wherein
the semiconductor layer comprises polycrystalline.
4. The structure according to claim 1 , wherein
source drain contacts in the second region of the semiconductor are in direct contact with epitaxially grown semiconductor material on the fin.
5. The structure according to claim 1 , wherein
a first pair of sidewall spacers are directly adjacent to the first stack, wherein the first pair of sidewall spacers serve as a gate dielectric in the first region; and
a second pair of sidewall spacers are directly adjacent to the second stack on the fin, and are also directly adjacent to epitaxially grown semiconductor material on the fin, wherein the first pair and the second pair of sidewall spacers comprise the same material and thickness.
6. The structure according to claim 5 , wherein
the first pair of sidewall spacers and the second pair of sidewall spacers comprises a dielectric.
7. A semiconductor structure comprising:
a semiconductor substrate comprising a first region and a second region, wherein
a first stack in the first region comprising a first dielectric layer, a first semiconductor layer, and a first mask, wherein a bottom surface of the first dielectric layer in the first region is essentially coplanar with a top surface of the semiconductor substrate in the first region, a top surface of the first dielectric layer in the first region is essentially coplanar with a bottom surface of the first semiconductor layer in the first region, and a top surface of the first semiconductor layer in the first region is essentially coplanar with a bottom surface of the first mask in the first region; and
a second stack in the second region comprising the first dielectric layer, and the first semiconductor layer, wherein a bottom surface of the first dielectric layer in the second region is essentially coplanar with a top surface of a fin only in the second region, a top surface of the first dielectric layer in the second region is essentially coplanar with a bottom surface of the first semiconductor layer in the second region, and a top surface of the first semiconductor layer in the second region is essentially coplanar with a bottom surface of the first mask in the second region, wherein
a top surface of the first mask in the first region is essentially coplanar with a top surface of the first mask in the second region; and
a top surface of the first semiconductor layer in the second region is essentially at the same height above a top surface of the semiconductor substrate as a top surface of the first mask in the first region, wherein the height is measured relative to a common surface of the semiconductor substrate.
8. The structure according to claim 7 , wherein the second region comprises an array of fin field effect transistors.
9. The structure according to claim 7 , wherein
the semiconductor layer comprises polycrystalline.
10. The structure according to claim 7 , wherein
source drain contacts in the second region of the semiconductor are in direct contact with epitaxially grown semiconductor material on the fin.
11. The structure according to claim 7 , wherein
a first pair of sidewall spacers are directly adjacent to the first stack, wherein the first pair of sidewall spacers serve as a gate dielectric in the first region; and
a second pair of sidewall spacers are directly adjacent to the second stack on the fin, and is also directly adjacent to epitaxially grown semiconductor material on the fin, wherein the first pair and the second pair of sidewall spacers comprise the same material and thickness.
12. The structure according to claim 7 , wherein
the first pair of sidewall spacers and the second pair of sidewall spacers comprises a dielectric.