IP Library Granted Patent US 9,997,409
Granted Patent B1
US 9,997,409 · App. 15/481,527 · Granted Jun 12, 2018

Fabricating contacts of a CMOS structure

Inventors: Lukas Czornomaz (Zurich, CH); Veeresh V. Deshpande (Zurich, CH); Vladimir Djara (Kilchberg, CH); Pouya Hashemi (White Plains, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
H01L21/823418H01L21/3065H01L21/30625H01L21/84H01L29/41783H01L29/66545H01L29/66553
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Quick Facts
Patent No.
US 9,997,409
App. No.
15/481,527
Granted
Jun 12, 2018
Kind
B1
Abstract

The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

Claims (7)

1. A computer program product, comprising:

a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code configured to cause one or more semiconductor processing apparatus to perform at least the following:

forming a gate stack structure on a channel layer of a substrate;

forming a raised source and a raised drain on the channel layer;

depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain, thereby creating a first void above the raised source and a second void above the raised drain adjacent to vertical edges of the gate stack structure;

etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer; and

forming contacts to the raised source and the raised drain.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2020
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: ELPIS TECHNOLOGIES INC.
Reel/Frame 052561/0161 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2017
From: CZORNOMAZ, LUKAS; DESHPANDE, VEERESH V.; DJARA, VLADIMIR; HASHEMI, POUYA
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 041927/0334 →