Dielectric gap fill evaluation for integrated circuits
Apparatus and methods for dielectric gap fill evaluations are provided. In one example, a method can comprise providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches. The method can also comprise depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate. Furthermore, the method can comprise etching the gap fill candidate material until a void within the first material is identified. Additionally, the method can comprise filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material to measure a leakage current of one or more pitches.
1. A method, comprising:
providing a gap fill substrate over one or more interlayer dielectric trenches of a dielectric layer and over a first material located in the one or more interlayer dielectric trenches;
depositing a gap fill candidate material within one or more gap fill substrate trenches of the gap fill substrate;
etching the gap fill candidate material within the one or more gap fill substrate trenches until a void within the gap fill candidate material is identified that exposes part of the first material; and
filling the one or more gap fill substrate trenches with a second material to form one or more contacts with the first material via at least the void to measure a leakage current of one or more pitches.
2. The method of claim 1 , further comprising:
performing lithography on the interlayer dielectric to create the one or more interlayer dielectric trenches.
3. The method of claim 1 , wherein the leakage current is measured as a function of voltage.
4. The method of claim 1 , wherein the leakage current is measured at the first material of a pitch of the one or more pitches.
5. The method of claim 1 , further comprising:
detecting the void associated with a pitch of the one or more pitches as a function of a line space.
6. The method of claim 1 , further comprising:
smoothing a surface of the interlayer dielectric and the first material via a chemical-mechanical planarization step.
7. The method of claim 1 , further comprising:
patterning the gap fill substrate to form the one or more gap fill substrate trenches.
8. A method, comprising:
depositing an interlayer dielectric on a silicon substrate;
depositing a first metal within one or more interlayer dielectric trenches of the interlayer dielectric;
etching a gap fill material, that has been deposited in one or more gap fill substrate trenches of a gap fill substrate disposed on the first metal and the interlayer dielectric, until a void within the gap fill material is reached that exposes part of the first metal; and
filling the one or more gap fill substrate trenches with a second metal to form one or more contacts with the first metal via at least the void to measure a leakage current between the first metal and the one or more contacts.
9. The method of claim 8 , further comprising:
patterning the interlayer dielectric to form the one or more interlayer dielectric trenches.
10. The method of claim 8 , further comprising:
patterning the gap fill substrate to form the one or more gap fill substrate trenches.
11. The method of claim 10 , wherein the patterning comprises a lithographic step to pattern the interlayer dielectric.
12. The method of claim 8 , further comprising:
smoothing a surface of the interlayer dielectric and the first metal via a chemical-mechanical planarization step.