Long channels for transistors
A method includes forming a gate on a first fin, a second fin, and a third fin arranged on a substrate. The method includes depositing a semiconductor material on the first fin, the second fin, and the third fin. The method further includes depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin. The method further includes forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin. The method includes depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.
1. A method for fabricating a semiconductor device, the method comprising:
forming a gate on a first fin, a second fin, and a third fin arranged on a substrate;
depositing a semiconductor material on the first fin, the second fin, and the third fin;
depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin;
forming a first trench and a second trench through the ILD on a first side of the gate, and a third trench and a fourth trench through the ILD on a second side of the gate, the second trench coupling the second fin to the third fin, and the third trench coupling the first fin to the second fin; and
depositing a metal in the first trench, the second trench, the third trench, and the fourth trench.
2. The method of claim 1 , wherein a pitch between the first fin and the second fin comprises at least 30 nanometers (nm).
3. The method of claim 1 , wherein depositing the semiconductor material comprises applying an epitaxial growth process.
4. The method of claim 1 , wherein subsequent to depositing the metal a channel is formed that crosses through the gate in three areas.
5. The method of claim 1 , wherein the first trench extends through the ILD to the semiconductor material on the first fin.
6. The method of claim 5 , wherein the second trench extends through the ILD to the semiconductor material on the second fin and the third fin.
7. The method of claim 1 , wherein the third trench extends through the ILD to the semiconductor material on the first fin and the second fin, and the fourth trench extends through the ILD to the semiconductor material on the third fin.
8. A method for fabricating a semiconductor device, the method comprising:
forming a gate on a first fin, a second fin, and a third fin arranged on a substrate;
removing a portion of the third fin to decrease a height of the third fin;
depositing a semiconductor material on the first fin, the second fin, and the third fin;
depositing an interlayer dielectric (ILD) on the first fin, the second fin, and the third fin;
forming a first trench through the ILD on a first side of the gate, and a second trench through the ILD on a second side of the gate, the first trench exposing the semiconductor material on the first fin and the second trench exposing the semiconductor material on the third fin; and
depositing a metal in the first trench and the second trench.
9. The method of claim 8 , wherein a pitch of the first fin and the second fin comprises less than 30 nanometers (nm).
10. The method of claim 8 , wherein depositing the semiconductor material comprises an epitaxial growth process.
11. The method of claim 10 , wherein the semiconductor material deposited on the first fin and the second fin overlaps one another.
12. The method of claim 8 , wherein after depositing the metal, a channel is formed that crosses through the gate in three areas.
13. The method of claim 8 , wherein the gate comprises a sacrificial gate material.
14. The method of claim 13 , wherein the gate is replaced with a metal gate stack before forming the first trench on the first side of the gate and the second trench on the second side of the gate.