Stress-induced CMOS device
View Patent ↗A semiconductor device including: a silicon dioxide layer; an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer; a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.
1. A semiconductor device comprising:
a silicon dioxide layer;
an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer;
a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer;
a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and
a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.
2. The semiconductor device of claim 1 , further comprising a second contact formed in the silicon dioxide layer, the second contact abutting the other one of the NFET or the PFET.
3. The semiconductor device of claim 1 , wherein the first contact abuts a source region of the NFET.
4. The semiconductor device of claim 1 , wherein the first contact includes a silicide portion and a metal portion.
5. The semiconductor device of claim 1 , further comprising a metal liner over the nitride stress liner.
6. The semiconductor device of claim 1 , wherein the nitride stress liner includes silicon nitride (SiN).
7. The semiconductor device of claim 1 , further comprising an oxide layer over the nitride stress liner.
8. A semiconductor device comprising:
a silicon dioxide layer;
an n-type field effect transistor (NFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer;
a p-type field effect transistor (PFET) including at least one recessed source/drain trench and located over a portion of the silicon dioxide layer;
a first spacer abutting the NFET and a second spacer abutting the PFET;
a nitride stress liner over the NFET and the PFET, the nitride stress liner filling the at least one recessed source/drain trench of the NFET and the at least one recessed source/drain trench of the PFET; and
a first contact formed in the silicon dioxide layer, the first contact abutting one of the NFET or the PFET.
9. The semiconductor device of claim 8 , further comprising a metal liner over the nitride stress liner.
10. The semiconductor device of claim 8 , further comprising an oxide layer over the nitride stress liner.
11. The semiconductor device of claim 8 , wherein the first contact includes a silicide portion and a metal portion.
12. The semiconductor device of claim 8 , further comprising a second contact abutting the other one of the NFET or the PFET.
13. The semiconductor device of claim 8 , further comprising:
a metal liner over the nitride stress liner; and
an oxide layer over the nitride stress liner.