Confined eptaxial growth for continued pitch scaling
A technique relates to manufacturing a finFET device. A plurality of first and second semiconductor fins are formed on a substrate. Gate stacks are formed on the substrate, each including a gate, a hard mask and an oxide layer. A dielectric spacer layer is deposited. A sacrificial fill material is deposited on the finFET device and planarized. A second hard mask is deposited, a trench area is patterned in the hard mask parallel to the first and second semiconductor fins, and the sacrificial fill material is anisotropically etched to create a trench. A dielectric wall is formed in the trench and the second hard mask and sacrificial fill material are removed.
1. A method for manufacturing a finFET device, the method comprising:
forming a plurality of first semiconductor fins on a substrate,
forming a plurality of second semiconductor fins on a substrate,
forming one or more gate stacks, each gate stack comprising a gate, a first hard mask, and an oxide layer;
depositing a low-k dielectric spacer layer on the finFET device;
depositing a sacrificial fill material on the finFET device;
planarizing the device with chemical mechanical planarization to the level of the oxide layer on top of the gate stacks;
depositing a second hard mask on the finFET device;
patterning a trench area in the second hard mask parallel to the first semiconductor fins and second semiconductor fins;
anisotropically etching the sacrificial fill material to create a trench;
forming a dielectric wall in the trench;
removing the second hard mask from the finFET device; and
selectively removing the sacrificial fill material.
2. The method according to claim 1 , wherein the first semiconductor fins are pFET fins and the second semiconductor fins are nFET fins.
3. The method according to claim 1 , wherein the first hard mask comprises a wet etch resistant material.
4. The method according to claim 3 , wherein the first hard mask comprises a composite silicon nitride/silicon oxide material.
5. The method according to claim 1 , wherein the low-k dielectric spacer layer is a SiBCN layer.
6. The method according to claim 1 , wherein the sacrificial fill material is amorphous silicon.
7. The method according to claim 1 , further comprising depositing a SiO, cap on the sacrificial fill material after planarizing the device with chemical mechanical planarization to the level of the liner on top of the gate stacks.
8. The method according to claim 1 , wherein the second hard mask comprises SiN.
9. The method according to claim 1 , wherein forming the dielectric wall comprises conducting atomic layer deposition.
10. The method according to claim 1 , wherein the dielectric wall comprises SiO.
11. The method according to claim 1 , further comprising growing at least one epitaxial layer on the first transistor or second transistor by an epitaxial growth process.
12. A method of manufacturing a finFET device, the method comprising:
patterning a plurality of first fins on a first transistor area and a plurality of second fins on a second transistor area;
forming two gate stacks, each gate stack comprising sacrificial gate material, a hard mask, and an oxide layer;
subtractively patterning a dielectric wall between the first fins and second fins; and
growing a first epitaxial layer on the first transistor area, wherein the first epitaxial layer is confined to the first transistor area by the dielectric wall.
13. The method of claim 12 , the method further comprising growing a second epitaxial layer on the second transistor area.
14. The method of claim 12 , wherein the dielectric wall comprises silicon oxide.