Self heating reduction for analog radio frequency (RF) device
A method of forming a semiconductor device includes forming a plurality of semiconductor fins from an upper semiconductor layer located on a first region of a bulk semiconductor substrate of a structure and then forming at least one gate structure straddling a portion of semiconductor fins. A portion of the lower semiconductor layer from beneath the upper semiconductor layer is then removed to form a vertical semiconductor portion which contacts the bulk semiconductor substrate and at least one of the semiconductor fins. A dielectric layer (e.g., a spacer layer) is then deposited over the structure and laterally surrounds the vertical semiconductor portion such that semiconductor fins and the at least one gate structure are partially isolated from the first region of the bulk semiconductor substrate by the dielectric layer.
1. A method of forming a semiconductor device, the method comprising:
forming a first shallow trench isolation (STI) trench in a first portion of a first semiconductor layer and a bulk semiconductor substrate; and
forming a second STI trench in a second portion of the first semiconductor layer and the bulk semiconductor substrate;
providing a first plurality of semiconductor fins that are spaced apart from each other and are located on a top surface of the first semiconductor layer, the first semiconductor material layer is present in at least a first region of the bulk semiconductor substrate, and wherein a lengthwise direction of the first STI trench and the second STI trench is parallel to a lengthwise direction of the first plurality of semiconductor fins;
forming at least one first region gate structure straddling over a portion of the first plurality of semiconductor fins, the at least one first region gate structure extending onto a portion of a top surface of the first STI trench and the second STI trench;
partially removing the first semiconductor layer from the first region to provide a vertical semiconductor material portion located beneath a portion of at least one of the first plurality of semiconductor fins that is overlapped by the at least one first region gate structure and to form a first region space, wherein the vertical semiconductor material portion contacts the bulk semiconductor substrate, the at least one of the first plurality of semiconductor fins the first STI trench and the second STI trench; and
depositing a first dielectric layer filling in the first region space and laterally surrounding the vertical semiconductor material portion such that the at least one first region gate structure and the first plurality of semiconductor fins are partially isolated from the first region of the bulk semiconductor substrate.
2. The method of claim 1 , wherein the vertical semiconductor material portion directly contacts the bottom surface of the at least one of the first plurality of semiconductor fins and the top surface of the first region of the bulk semiconductor substrate and provides a heat dissipation path from the at least one first region gate structure and the at least one of the first plurality of semiconductor fins to the first region of the bulk semiconductor substrate.
3. The method of claim 1 , wherein the first dielectric layer has a top surface that is coplanar with a top surface of the vertical semiconductor material portion.
4. The method of claim 1 , wherein the vertical semiconductor material portion is located beneath a channel portion of each semiconductor fin of the first plurality of semiconductor fins.
5. The method of claim 1 , wherein a height of the vertical semiconductor material portion is equal to a height of the first dielectric layer.
6. The method of claim 1 , wherein the vertical semiconductor material portion is pillar shaped.
7. The method of claim 1 , wherein the vertical semiconductor material portion is located greater than 5 nm from an edge of the at least one first region gate structure.
8. The method of claim 1 , wherein the bulk semiconductor substrate includes silicon, wherein the first semiconductor layer includes one of silicon germanium (SiGe) or indium phosphide (InP), and wherein the each semiconductor fin of the first plurality of semiconductor fins includes one of silicon or indium arsenide (InAs).
9. The method of claim 1 , wherein the first semiconductor material layer is also present in a second region of the bulk semiconductor substrate and said method further comprises:
providing a second plurality of semiconductor fins that are spaced apart from each other and are located on the top surface of the first semiconductor layer in the second region of the bulk semiconductor substrate;
forming at least one second region gate structure straddling over a portion of the second plurality of semiconductor fins;
removing the entire first semiconductor layer in the second region to form a second region space between a top surface of the second region of the bulk semiconductor substrate and a bottom surface of the second plurality of semiconductor fins and a bottom surface of the at least one second region gate structure; and
depositing a second dielectric layer filling in the entire second region space such that the second plurality of semiconductor fins and the at least one second gate structure are fully isolated from the second region of the bulk semiconductor substrate by the second dielectric layer, and
wherein a width of the at least one second region gate structure is less than a width of the at least one first region gate structure.
10. The method of claim 9 , wherein prior to forming the at least one second region gate structure, the method further comprising:
forming a third shallow trench isolation (STI) trench in a third portion of the first semiconductor layer and the bulk semiconductor substrate; and
forming a fourth STI trench in a fourth portion of the first semiconductor layer and the bulk semiconductor substrate, wherein a lengthwise direction of the third STI trench and the fourth STI trench is parallel to a lengthwise direction of the second plurality of semiconductor fins.
11. The method of claim 10 , wherein the at least one second region gate structure is formed by:
forming a second conductive layer on the second plurality of semiconductor fins and on the third STI trench and the fourth STI trench;
forming a second region hard mask layer on the second conductive layer;
patterning the second region hard mask layer to form at least one second region hard mask on the second conductive layer; and
patterning the second conductive layer using the at least one second region hard mask as an etching mask to form the at least one second region gate structure, wherein the at least one second region hard mask is located on a top surface of the at least one second region gate structure, and
wherein the second dielectric layer deposited also covers and contacts a top surface and opposing sidewalls of the at least one second region hard mask, covers and contacts opposing sidewalls of the at least one second region gate structure, and covers and contacts each portion of the second plurality of semiconductor fins not covered by the at least one second region gate structure.
12. The method of claim 11 , further comprising forming a second gate spacer on the opposing sidewalls of the at least one second region gate structure and on a lower portion of the opposing sidewalls of the at least one second region hard mask by:
etching portions of the second dielectric layer located on the top surface of the at least one second region hard mask and from an upper portion of the opposing sidewalls of the at least one second region hard mask; and
etching portions of the second dielectric layer from areas of the second plurality of semiconductor fins not overlapped with the at least one second region gate structure the second dielectric layer comprising at least silicon nitride.
13. The method of claim 12 , wherein the second region of the bulk semiconductor substrate of the second structure includes silicon, wherein the first semiconductor layer includes one of silicon germanium (SiGe) or indium phosphide (InP), and wherein the semiconductor fins of the second plurality of semiconductor fins includes one of silicon or indium arsenide (InAs).