Vertical transport FET with two or more gate lengths
A method for forming a device with multiple gate lengths includes forming a gate stack on vertical fins. A cutting mask formed on the gate stack is etched to include two or more different heights. Gate structures with two or more gate lengths are etched by employing the two or more different heights in the cutting mask as an etch mask. The cutting mask is removed. A top source/drain regions is formed on top of the vertical fins.
1. A method for forming a device with multiple gate lengths, comprising:
forming a gate stack on vertical fins with a bottom source/drain region on a substrate;
forming a photoresist mask on the gate stack to accommodate two gate lengths;
etching a cutting mask formed on the photoresist mask to include two different heights;
etching the gate stack to form gate structures with the two gate lengths by employing the two different heights in the cutting mask as an etch mask;
removing the cutting mask; and
forming a top source/drain region on top of the vertical fins.
2. The method as recited in claim 1 , wherein heights of the gate structures combined with heights of the top source/drain region on the vertical fins are equal between all the vertical fins.
3. The method as recited in claim 1 , wherein the gate stack that includes a gate dielectric layer and a work function metal layer.
4. The method as recited in claim 1 , wherein the photoresist mask includes a grey tone photoresist mask.
5. The method as recited in claim 1 , wherein forming the top source/drain region includes epitaxially growing the top source/drain region to different depths in trenches on the vertical fins.
6. The method as recited in claim 5 , wherein forming the top source/drain region further includes forming a top resist mask patterned to accommodate two or more implantation depths, etching a top cutting mask using the pattern in the top resist mask, and forming a top source/drain extension region.
7. The method as recited in claim 6 , wherein forming the top source/drain extension region includes performing an ion implantation process into the vertical fins down to the gate structure by employing the top mask.
8. A method for forming a device with multiple gate lengths, comprising:
forming a cutting mask over a conformal gate stack on vertical fins with a bottom source/drain region on a substrate;
forming a resist layer over the cutting mask;
forming a resist mask by patterning the resist layer to accommodate two gate lengths;
etching the cutting mask below using the pattern in the resist mask to include two different heights in the cutting mask;
forming gate structures with the two gate lengths employing the two different heights in the cutting mask to etch back the conformal gate stack to the two gate lengths;
removing the cutting mask;
forming a spacer and an etch mask;
patterning the etch mask to expose the vertical fins;
forming trenches to different depths accommodated by the etch mask by etching the spacer, a hard mask on vertical fins of the gate structures, and the vertical fins of the gate structures; and
forming a top source/drain region in the trenches on the gate structures.
9. The method as recited in claim 8 , wherein heights of the gate structures combined with heights of the top source/drain region on the gate structure are equal between all the gate structures.
10. The method as recited in claim 8 , wherein the conformal gate stack that includes a gate dielectric layer and a work function metal layer.
11. The method as recited in claim 8 , wherein patterning the resist layer includes forming a photoresist mask to accommodate at least two of gate lengths.
12. The method as recited in claim 11 , wherein the photoresist mask includes a grey tone photoresist mask.
13. The method as recited in claim 8 , wherein forming the top source/drain region includes epitaxially growing the top source/drain region in the trenches until the top source/drain regions have the different depths accommodated by the etch mask.